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    Semiconductor memory devices and memory systems including the same
    11.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US09552867B2

    公开(公告)日：2017-01-24

    申请号：US14588496

    申请日：2015-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Uk-Song Kang ,  Kwang-Il Park ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jae-Youn Youn

    IPC: G06F3/06 ,  G11C11/408 ,  G11C5/02 ,  G11C7/02

    CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4085

    Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

    Abstract translation: 半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。 存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。 控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。 控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。 第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。 因此，可以补偿增加的定时参数，并且可以增加并行性。

    Semiconductor memory device and memory system including the same
    12.
    发明授权
    Semiconductor memory device and memory system including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US09064603B1

    公开(公告)日：2015-06-23

    申请号：US14185302

    申请日：2014-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Youn Youn ,  Su-A Kim ,  Hyo-Jin Choi ,  Chul-Woo Park ,  Hak-Soo Yu

    IPC: G11C7/10 ,  G11C11/409

    CPC classification number: G11C11/40626 ,  G06F11/106 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/22 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409

    Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.

    Abstract translation: 半导体存储器件包括存储单元阵列和控制逻辑。 存储单元阵列包括第一和第二子阵列，第一子阵列包括第一组阵列阵列，而第二子阵列包括第二组阵列阵列。 上部和下部排列阵列中的每一个包括相对于彼此具有不同定时参数的第一和第二部分。 控制逻辑控制对第一和第二部分的访问，使得在第一和第二部分上执行读/写操作。

    Managing memory device with processor-in-memory circuit to perform memory or processing operation
    13.
    发明授权
    Managing memory device with processor-in-memory circuit to perform memory or processing operation 有权

    公开(公告)号：US11635962B2

    公开(公告)日：2023-04-25

    申请号：US16814462

    申请日：2020-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

    IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

    Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

    Stacked memory device and a memory chip including the same
    17.
    发明授权
    Stacked memory device and a memory chip including the same 有权

    公开(公告)号：US10331354B2

    公开(公告)日：2019-06-25

    申请号：US15617450

    申请日：2017-06-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hak-Soo Yu ,  Je-Min Ryu ,  Reum Oh ,  Pavan Kumar Kasibhatla ,  Seok-In Hong

    IPC: G06F3/06 ,  G11C5/02 ,  G11C5/06 ,  G11C5/04

    Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

    Memory device and method of refreshing in a memory device
    19.
    发明授权
    Memory device and method of refreshing in a memory device 有权
    存储设备和在存储设备中刷新的方法

    公开(公告)号：US09336851B2

    公开(公告)日：2016-05-10

    申请号：US14168793

    申请日：2014-01-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hak-Soo Yu ,  Jung-Bae Lee

    IPC: G11C11/406

    CPC classification number: G11C11/406 ,  G11C11/40603

    Abstract: In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed.

    Abstract translation: 在具有多个页面的存储装置中进行刷新的方法中，生成与在监视期间之后被更新的页面对应的候补刷新地址。 在监视期间监视是否处理候选刷新地址的活动命令。 如果在监视期间处理候选刷新地址的活动命令，则跳过该页面的计划刷新。 如果在监视期间没有处理候选刷新地址的活动命令，则执行预定的刷新操作。

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