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    METHODS AND DEVICES TO INCREASE MEMORY DEVICE DATA RELIABILITY
    11.
    发明申请
    METHODS AND DEVICES TO INCREASE MEMORY DEVICE DATA RELIABILITY 审中-公开
    增加存储器件数据可靠性的方法和设备

    公开(公告)号：US20140129891A1

    公开(公告)日：2014-05-08

    申请号：US14154859

    申请日：2014-01-14

    Applicant: Seagate Technology LLC

    Inventor： Navneeth Kankani ,  Mark Allen Gaertner ,  Rodney Virgil Bowman ,  Ryan James Goss ,  David Scott Seekins ,  Tong Shirh Stone

    IPC: G06F11/10

    CPC classification number: G06F11/102 ,  G06F11/1012 ,  G11C29/52

    Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.

    Abstract translation: 将第一数据集写入被识别为具有较高数据可靠性的第一存储器单元，并且将第二数据组写入被识别为具有比第一存储器单元更低的数据可靠性的第二存储器单元。 在一些情况下，第二数据集可以包括有助于读取和/或解码第一数据集的元数据或冗余信息。 写入第二数据集的动作增加了第一数据集的数据可靠性。 第二数据集可以是空模式，例如所有擦除位。

    Threshold voltage calibration using reference pattern detection
    13.
    发明授权
    Threshold voltage calibration using reference pattern detection 有权
    使用参考图案检测的阈值电压校准

    公开(公告)号：US08971111B2

    公开(公告)日：2015-03-03

    申请号：US13900718

    申请日：2013-05-23

    Applicant: Seagate Technology LLC

    Inventor： Mai A. Ghaly ,  Rodney Virgil Bowman

    IPC: G11C11/34 ,  G11C16/34

    CPC classification number: G06F11/1008 ,  G06F11/1048 ,  G11C7/14 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

    Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.

    Abstract translation: 存储器控制器识别固态存储器单元的存储器单元的主要类型的误差。 计算误差类型差分。 误差类型差是电荷损失误差的数量与存储器单元的充电增益误差的数量之差。 计算VT偏移误差差。 VT偏移误差差是在第一VT偏移处的主要类型的错误的数量和在第二VT偏移处的主要类型的错误的数量之间的差。 使用误差类型差和VT偏移误差的比率来确定VT偏移。

    THREE DIMENSIONAL FLOATING GATE NAND MEMORY
    14.
    发明申请
    THREE DIMENSIONAL FLOATING GATE NAND MEMORY 有权
    三维浮动门NAND存储器

    公开(公告)号：US20150011062A1

    公开(公告)日：2015-01-08

    申请号：US14264605

    申请日：2014-04-29

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Antoine Khoueir ,  YoungPil Kim ,  Rodney Virgil Bowman

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

    CPC classification number: H01L29/66825 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/7889

    Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.

    Abstract translation: 存储器阵列，其包括具有通道的第一存储器单元; 第一绝缘子; 一个浮动门; 第二绝缘体; 以及控制栅极，其中所述第一绝缘体位于所述沟道和所述浮置栅极之间，所述第二绝缘体位于所述浮置栅极和所述控制栅极之间; 以及具有通道的第二存储单元; 第一绝缘子; 一个浮动门; 第二绝缘体; 以及控制栅极，其中所述第一绝缘体位于所述沟道和所述浮置栅极之间，所述第二绝缘体位于所述浮置栅极和所述控制栅极之间，其中所述第一存储器单元和所述第二存储器单元彼此平行地定位。

    FAULT TOLERANT CONTROL LINE CONFIGURATION
    16.
    发明申请
    FAULT TOLERANT CONTROL LINE CONFIGURATION 有权
    故障控制线路配置

    公开(公告)号：US20140119123A1

    公开(公告)日：2014-05-01

    申请号：US13665443

    申请日：2012-10-31

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： YoungPil Kim ,  Rodney Virgil Bowman

    IPC: G11C16/04 ,  G11C5/06

    CPC classification number: G11C29/702 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C29/804

    Abstract: A fault tolerant control line configuration useful in a variety of solid state memories such as but not limited to a flash memory. In accordance with some embodiments, an apparatus includes a plurality of memory cells, and a fault tolerant control line. The control line has an elongated first conductive path connected to each of the plurality of memory cells. An elongated second conductive path is disposed in a parallel, spaced apart relation to the first conductive path. A plurality of conductive support members are interposed between the first and second conductive paths to support the second conductive path above the first conductive path.

    Abstract translation: 用于各种固态存储器（例如但不限于闪速存储器）的容错控制线配置。 根据一些实施例，装置包括多个存储器单元和容错控制线。 控制线具有连接到多个存储单元中的每一个的细长的第一导电路径。 细长的第二导电路径以与第一导电路径平行的间隔开的关系设置。 多个导电支撑构件插入在第一和第二导电路径之间以支撑第一导电路径上方的第二导电路径。

    Partial reprogramming of solid-state non-volatile memory cells
    17.
    发明授权
    Partial reprogramming of solid-state non-volatile memory cells 有权
    固态非易失性记忆体的部分重编程

    公开(公告)号：US09378830B2

    公开(公告)日：2016-06-28

    申请号：US13943441

    申请日：2013-07-16

    Applicant: Seagate Technology LLC

    Inventor： Antoine Khoueir ,  Varun Voddi ,  Rodney Virgil Bowman

    IPC: G11C16/12 ,  G11C16/14 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C13/00

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3431

    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the programmed state of a selected memory cell in the set is detected, and the selected memory cell is partially reprogrammed to return the selected memory cell to the associated initial programmed state.

    Abstract translation: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据一些实施例，将数据写入一组固态非易失性存储器单元，使得该组中的每个存储单元被写入相关联的初始编程状态。 检测到集合中所选择的存储器单元的编程状态的漂移，并且所选存储单元被部分重新编程以使所选择的存储单元返回到相关的初始编程状态。

    Temperature tracking to manage threshold voltages in a memory
    18.
    发明授权
    Temperature tracking to manage threshold voltages in a memory 有权
    温度跟踪来管理存储器中的阈值电压

    公开(公告)号：US09330790B2

    公开(公告)日：2016-05-03

    申请号：US14261560

    申请日：2014-04-25

    Applicant: Seagate Technology LLC

    Inventor： Young Pil Kim ,  Rodney Virgil Bowman ,  Caitlin Marie Race ,  Don R. Bloyer

    IPC: G11C16/04 ,  G11C29/50 ,  G11C7/04 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42

    CPC classification number: G11C29/50004 ,  G11C7/04 ,  G11C16/349 ,  G11C29/028 ,  G11C29/42

    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, a first data access operation is conducted on a memory cell and a first temperature associated with the memory cell and associated with the first data access operation is measured. A second temperature associated with the memory cell is measured. At least one operational parameter is adjusted responsive to the first and second temperatures associated with the memory cell. A second data access operation is conducted on the memory cell using the adjusted operational parameter.

    Abstract translation: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据各种实施例，对存储器单元执行第一数据访问操作，并且测量与存储器单元相关联并与第一数据访问操作相关联的第一温度。 测量与存储器单元相关联的第二温度。 响应于与存储器单元相关联的第一和第二温度来调整至少一个操作参数。 使用经调整的操作参数对存储器单元进行第二数据访问操作。

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