公开(公告)号：US20170077034A1

公开(公告)日：2017-03-16

申请号：US15358217

申请日：2016-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hyeonuk Kim

IPC: H01L23/535 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L23/535 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width.

Abstract translation: 半导体器件包括设置在衬底的跨接区域中并沿第一方向延伸的第一栅电极，设置在第一栅极两侧的第一源/漏区和将第一栅电极和第二栅电极电连接的连接接点， 第一源极/漏极区彼此。 连接触点包括设置在第一栅电极的两侧并连接到第一源/漏区的第一子触点和沿与第一方向相交的第二方向延伸的第二副触点。 第二子触点连接到第一子触点并与第一栅电极的顶表面接触。 在第一方向上，每个第一子接触具有第一宽度，而第二子接触具有小于第一宽度的第二宽度。

公开(公告)号：US09536835B2

公开(公告)日：2017-01-03

申请号：US14625015

申请日：2015-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hyeonuk Kim

IPC: H01L29/78 ,  H01L27/08 ,  H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L23/535 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width.

Abstract translation: 半导体器件包括设置在衬底的跨接区域中并沿第一方向延伸的第一栅电极，设置在第一栅极两侧的第一源/漏区和将第一栅电极和第二栅电极电连接的连接接点， 第一源极/漏极区彼此。 连接触点包括设置在第一栅电极的两侧并连接到第一源/漏区的第一子触点和沿与第一方向相交的第二方向延伸的第二副触点。 第二子触点连接到第一子触点并与第一栅电极的顶表面接触。 在第一方向上，每个第一子接触具有第一宽度，而第二子接触具有小于第一宽度的第二宽度。

公开(公告)号：US20160020148A1

公开(公告)日：2016-01-21

申请号：US14668430

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hwi-Chan Jun

IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/45 ,  H01L21/285 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53266 ,  H01L23/535 ,  H01L28/24 ,  H01L29/456 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

公开(公告)号：US09093422B2

公开(公告)日：2015-07-28

申请号：US14245007

申请日：2014-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongun Kim ,  Dong-Hyun Kim ,  Hyun-Seung Song

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L2029/7858

Abstract: A semiconductor device includes a fin portion protruding from a substrate. The fin portion includes a base part, an intermediate part on the base part, and a channel part on the intermediate part. A width of the intermediate part is less than a width of the base part and greater than a width of the channel part. A gate electrode coves both sidewalls and a top surface of the channel part, and a device isolation pattern covers both sidewalls of the base part and both sidewalls of the intermediate part.

Abstract translation: 半导体器件包括从衬底突出的鳍部。 翅片部分包括基部，基部上的中间部分和中间部分上的通道部分。 中间部分的宽度小于基部的宽度并且大于通道部分的宽度。 栅极电极使沟道部分的两个侧壁和顶表面均匀，并且器件隔离图案覆盖基部的两个侧壁和中间部分的两个侧壁。

公开(公告)号：US20130344666A1

公开(公告)日：2013-12-26

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。

公开(公告)号：US12009398B2

公开(公告)日：2024-06-11

申请号：US17932851

申请日：2022-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L29/401

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US11978775B2

公开(公告)日：2024-05-07

申请号：US17841873

申请日：2022-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Hyun-Seung Song ,  Yeongchang Roh ,  Heonjong Shin ,  Sora You ,  Yongsik Jeong

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/45

CPC classification number: H01L29/41775 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/456

Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.

公开(公告)号：US11380791B2

公开(公告)日：2022-07-05

申请号：US16225122

申请日：2018-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hyo-Jin Kim ,  Kyoung-Mi Park ,  Hwi-Chan Jun ,  Seung-Seok Ha

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

Abstract: A semiconductor device includes a first impurity region, a channel pattern, a second impurity region, a gate structure, a first contact pattern, a second contact pattern and a spacer. The first impurity region may be formed on a substrate. The channel pattern may protrude from an upper surface of the substrate. The second impurity region may be formed on the channel pattern. The gate structure may be formed on a sidewall of the channel pattern and the substrate adjacent to the channel pattern, and the gate structure may include a gate insulation pattern and a gate electrode. The first contact pattern may contact an upper surface of the second impurity region. The second contact pattern may contact a surface of the gate electrode. The spacer may be formed between the first and second contact patterns. The spacer may surround a portion of a sidewall of the second contact pattern, and the spacer may contact a sidewall of each of the first and second contact patterns.

公开(公告)号：US09679991B2

公开(公告)日：2017-06-13

申请号：US14670324

申请日：2015-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi-Chan Jun ,  Deok-Han Bae ,  Hyun-Seung Song ,  Seung-Seok Ha

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656

Abstract: Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.

公开(公告)号：US09406770B2

公开(公告)日：2016-08-02

申请号：US14668430

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hwi-Chan Jun

IPC: H01L21/8234 ,  H01L29/45 ,  H01L21/285 ,  H01L49/02 ,  H01L29/66 ,  H01L27/06 ,  H01L29/51

CPC classification number: H01L27/0629 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53266 ,  H01L23/535 ,  H01L28/24 ,  H01L29/456 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括提供包括晶体管区域和电阻器区域的衬底，在电阻器区域中的衬底上形成伪栅极结构和下层间绝缘层; 形成具有缓冲绝缘图案的电阻器结构，电阻元件和顺序地设置在下层间绝缘层上的蚀刻延迟图案; 以及形成电阻器接触结构，其被配置为穿过所述蚀刻延迟图案并与所述电阻器元件接触。