公开(公告)号：US10950521B2

公开(公告)日：2021-03-16

申请号：US16566380

申请日：2019-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Ok Na ,  Jongkook Kim ,  Hyo-Chang Ryu ,  Jin-woo Park ,  BongJin Son ,  Jangwoo Lee

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

公开(公告)号：US20180145006A1

公开(公告)日：2018-05-24

申请号：US15856800

申请日：2017-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Ok NA ,  Jongkook Kim ,  Hyo-Chang Ryu ,  Jin-woo Park ,  BongJin Son ,  Jangwoo Lee

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/50 ,  H01L23/498

CPC classification number: H01L23/373 ,  H01L21/563 ,  H01L23/367 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/207

Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

公开(公告)号：US09425156B2

公开(公告)日：2016-08-23

申请号：US14283828

申请日：2014-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha Jung ,  Jongkook Kim ,  Bona Baek ,  Heeseok Lee ,  Kyoungsei Choi

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83471 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

Abstract translation: 半导体封装包括其中具有通孔的第一板，设置在第一板的第一表面上的至少一个互连层，以及至少一个半导体芯片，该半导体芯片设置在由通孔限定的空间中的至少一个互连层上 并且电连接到所述至少一个互连层。 所述封装还包括设置在所述至少一个半导体芯片上的第二板和所述第一板的与所述第一表面相对的一侧上的所述第一板的第二表面，以及设置在所述第一板的第二表面上的至少一个导电垫 并且电连接到所述至少一个互连层。

公开(公告)号：US20130130472A1

公开(公告)日：2013-05-23

申请号：US13741466

申请日：2013-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Do LEE ,  Jongkook Kim ,  SeokWon Lee ,  Jaesik Lee ,  Hohyeuk Im ,  Su-Min Park

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract translation: 提供了一种半导体芯片。 半导体芯片包括包括主芯片区域和围绕主芯片区域的划线通道区域的半导体衬底。 绝缘层设置在半导体衬底上。 保护环设置在划线区域的绝缘层中。 防护环围绕主芯片区域的至少一部分。 保护环的脆性大于绝缘层的脆性。