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    Semiconductor package and method of manufacturing the same
    12.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US11942446B2

    公开(公告)日：2024-03-26

    申请号：US17165429

    申请日：2021-02-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyoeun Kim ,  Sunkyoung Seo ,  Seunghoon Yeon ,  Chajea Jo

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

    CPC classification number: H01L24/14 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L2224/14181

    Abstract: A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

    Semiconductor package
    14.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11735566B2

    公开(公告)日：2023-08-22

    申请号：US17375511

    申请日：2021-07-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ohguk Kwon ,  Namhoon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

    IPC: H01L25/065 ,  H01L23/538

    CPC classification number: H01L25/0657 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

    Abstract: A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.

    SEMICONDUCTOR PACKAGE
    16.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220216186A1

    公开(公告)日：2022-07-07

    申请号：US17705872

    申请日：2022-03-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguk Han ,  Chajea Jo ,  Hyoeun Kim ,  Sunkyoung Seo

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

    Semiconductor packages including stacked substrates and penetration electrodes
    17.
    发明授权
    Semiconductor packages including stacked substrates and penetration electrodes 有权

    公开(公告)号：US11222873B2

    公开(公告)日：2022-01-11

    申请号：US16936882

    申请日：2020-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

    IPC: H01L25/065 ,  H01L23/00

    Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

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