公开(公告)号：US07241685B2

公开(公告)日：2007-07-10

申请号：US10390413

申请日：2003-03-18

申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hideo Miura ,  Shinji Nishihara ,  Masashi Sahara

发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hideo Miura ,  Shinji Nishihara ,  Masashi Sahara

IPC分类号： H01L21/44

CPC分类号： H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

摘要翻译： 提供一种具有降低短路可能性的布线结构的半导体器件及其制造方法。 此外，提供了具有高可靠性的半导体器件。 此外，提供了一种具有高产率的半导体器件。 在半导体衬底的一个主表面侧形成布线，并且具有相邻导体层和主布线层的叠层结构。 主配线层包含一个添加的元素以防止迁移。 相邻的导体层由用于防止主要构成元素和主配线层的添加元素扩散到相邻导体层下方的基板中的材料形成，并且添加元素在靠近界面处的位置的浓度 与相邻的导体层间隔开的主配线层的添加元素的浓度相比，相邻的导体层和主布线层的电位低。

公开(公告)号：US07217971B2

公开(公告)日：2007-05-15

申请号：US10848473

申请日：2004-05-17

申请人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

发明人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L31/119

CPC分类号： H01L21/823462 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/823412 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78696

摘要： Diffusion layers 2–5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2–5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

摘要翻译： 在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8,9，以便成为MOS晶体管。 氧化锆或氧化铪被用作栅介质膜6,7的主要成分。 栅介质膜6,7例如通过CVD形成。 作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。 在使用表面为（111）晶面的基板的情况下，在使用表面为（001）晶面的硅基板的情况下，氧的扩散系数小于1/100，氧气 扩散被控制。 因此，控制氧扩散，防止漏电流的产生，提高性能。 实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

公开(公告)号：US20060125116A1

公开(公告)日：2006-06-15

申请号：US11350919

申请日：2006-02-10

申请人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

发明人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

IPC分类号： H01L23/48

CPC分类号： H01L23/3157 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.

摘要翻译： 多芯片模块具有至少两个半导体芯片。 每个半导体芯片具有半导体芯片的芯片电极，用于与芯片电极电连接的导电互连，用于与互连电连接的导电焊盘，设置在焊盘上的外部端子以及介于两者之间的应力松弛层 土地和半导体芯片。 半导体芯片通过外部端子放置在安装板上。 位于所述第二半导体芯片的最外端部的最外侧端子之间的距离小于第一半导体芯片的距离。

公开(公告)号：US20050227384A1

公开(公告)日：2005-10-13

申请号：US10519175

申请日：2002-09-26

申请人： Kouta Nagano ,  Hideo Miura ,  Akihiro Yaguchi

发明人： Kouta Nagano ,  Hideo Miura ,  Akihiro Yaguchi

IPC分类号： H01L21/56 ,  H01L23/31 ,  G01R31/26

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/05599

摘要： In a production of a semiconductor device, after a step in which a thermosetting resin is thermally cured to seal a semiconductor chip with the resin and before a step in which a characteristic of the semiconductor chip is inspected, the thermosetting resin is baked at a temperature higher than the resin sealing temperature in said resin sealing step.

摘要翻译： 在半导体器件的制造中，在将热固性树脂热固化以与树脂密封半导体芯片的步骤之后，并且在检查半导体芯片的特性的步骤之前，将热固性树脂在温度 高于所述树脂密封步骤中的树脂密封温度。

公开(公告)号：US06949387B2

公开(公告)日：2005-09-27

申请号：US10626718

申请日：2003-07-25

申请人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

发明人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

IPC分类号： H01L21/762 ,  H01L27/08 ,  H01L21/66

CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/0802

摘要： A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.

摘要翻译： 提供了一种半导体器件的技术，其包括在器件形成区域上形成电路区域和半导体衬底上的器件隔离区域，器件隔离区域的宽度与其相邻电路区域的宽度的比率被设置为2至 还提供了一种设计方法，包括进行测量，例如衬垫氧化膜和氮化物膜的厚度，氮化物膜的内部应力，器件形成和隔离区域的宽度，蚀刻部分的深度 的用于在器件隔离区域中形成沟槽的氮化物膜，由于热氧化而在沟槽附近进行导电应力分析，以及与器件形成区域的宽度和不引导的器件隔离区域的设定值 发生脱位。

公开(公告)号：US06876073B2

公开(公告)日：2005-04-05

申请号：US10260348

申请日：2002-10-01

申请人： Hideo Miura ,  Ryuji Kohno

发明人： Hideo Miura ,  Ryuji Kohno

IPC分类号： H01R33/76 ,  G01R1/073 ,  H01L21/66 ,  H01L23/00 ,  H01L23/485 ,  H01R13/533 ,  H05K3/32 ,  H01L23/02 ,  H01L23/34

CPC分类号： H01L24/05 ,  G01R1/073 ,  H01L2224/05624 ,  H01L2224/85424 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor device superior in heat dissipation in which the exchanging of chips can be readily performed is realized by mounting, through means distinct from bonding or connecting, a LSI chip on an interconnection substrate having substantially no difference in thermal conductivity between the LSI chip and the substrate. The semiconductor device is provided on an interconnection substrate 6 with electrode terminals 7 of cantilever structure, an interconnection layer 8 for electrical connection among the electrode terminals 7, an interconnection layer 12 for electrical connection to outer portions, and fitting portions 9 formed in a cover 5, the substrate 6 and the cover 5 being connected by the fitting portions. The chips 1 and 2 are electrically contacted through the terminals 7 without using any bonding or connecting, so that the mounting and detachment of the cover 5 and the substrate can be readily performed.

摘要翻译： 通过在LSI芯片和LSI芯片之间基本上没有导热性差异的互连基板上安装LSI芯片，通过不同于粘接或连接的方式，实现了易于进行芯片交换的散热优良的半导体器件。 基质。 半导体器件设置在具有悬臂结构的电极端子7的互连基板6上，用于在电极端子7之间电连接的互连层8，用于与外部电连接的互连层12以及形成在盖子中的嵌合部分9 如图5所示，基板6和盖5通过嵌合部连接。 芯片1和2通过端子7电接触而不使用任何结合或连接，从而可以容易地执行盖5和基板的安装和拆卸。

公开(公告)号：US06858515B2

公开(公告)日：2005-02-22

申请号：US10638485

申请日：2003-08-12

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76232 ,  H01L29/0657

摘要： A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

摘要翻译： 在上沟槽边缘处的晶体管中没有电故障的半导体器件可以通过简化的工艺制造，包括在半导体衬底的电路形成侧形成衬垫氧化膜的基本步骤; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化呈现膜和衬垫氧化膜，从而暴露半导体衬底的表面; 水平地凹陷衬垫氧化膜，通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 氧化在半导体衬底中形成的沟槽; 在氧化沟槽中嵌入嵌入隔离膜; 去除形成在防氧化膜上的嵌入隔离膜; 去除形成在半导体衬底的电路形成侧的氧化防止膜; 以及去除形成在半导体衬底的电路形成侧的衬垫氧化膜，其中如果需要，可以获得具有曲率的圆形上沟槽边缘，通过对半导体衬底的暴露表面进行各向同性蚀刻并且使衬垫的水平凹陷 氧化膜在沟槽氧化之前，因此只需要一个氧化步骤。

公开(公告)号：US06646350B2

公开(公告)日：2003-11-11

申请号：US09922230

申请日：2001-08-03

申请人： Naotaka Tanaka ,  Hideo Miura ,  Yoshiyuki Kado ,  Ikuo Yoshida ,  Takahiro Naito

发明人： Naotaka Tanaka ,  Hideo Miura ,  Yoshiyuki Kado ,  Ikuo Yoshida ,  Takahiro Naito

IPC分类号： H01L2352

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12044 ,  H01L2924/00

摘要： In order to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric connection between each of bump pads formed on LSI chips and each of electrode pads formed on an interconnection substrate, within an guaranteed temperature range, a thermal expansion coefficient of an adhesive (3) is in the range of 20 to 60 ppm, and an elastic modulus of a build-up portion (6) is in the range of 5 to 10 GPa. Further, the build-up portion (6) is constituted by a multi-layer build-up substrate in which buid-up portion a peak value (a glass transition temperature) of a loss coefficient exists within a range of 100° C. to 250° C. and does not exist within a range of 0° C. to 100° C. By setting or selecting the physical properties in the manner disclosed above, it is possible to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric bonding between the bump pads (2) formed on the LSI chips (1) and the electrode pads (4) on the interconnection substrate (5) within an guaranteed temperature range.

摘要翻译： 为了实现能够保持高可靠性的半导体器件及其制造方法，在形成在LSI芯片上的每个凸块焊盘和形成在互连基板上的每个电极焊盘之间的电连接在保证的温度范围内， 粘合剂（3）的膨胀系数在20〜60ppm的范围内，积聚部（6）的弹性模量在5〜10GPa的范围内。 此外，积存部（6）由多层积层基板构成，在该多层积层基板中，增益部分的损耗系数的峰值（玻璃化转变温度）存在于100℃〜 250℃，并且不存在于0℃至100℃的范围内。通过以上述方式设置或选择物理性质，可以实现可以保持的半导体器件及其制造方法 在保证温度范围内，形成在LSI芯片（1）上的凸块焊盘（2）和互连基板（5）上的电极焊盘（4）之间的电连接具有高可靠性。

公开(公告)号：US06639263B2

公开(公告)日：2003-10-28

申请号：US10255714

申请日：2002-09-27

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L27108

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

摘要翻译： 本发明的目的是提供一种具有存储电容器和使用铜作为主导电膜的布线的高可靠性半导体器件。 根据上述目的，本发明提供一种半导体器件，包括：半导体衬底; 形成在所述半导体基板的所述主面侧的作为第一电极的保持电容器和布置成放置电容器绝缘膜的第二电极; 形成在所述半导体衬底的主表面侧并且包括所述铜（Cu）元件的布线导体; 以及形成在所述布线导体的表面上的第一膜; 其中构成第一膜的材料和构成第一电极和/或第二电极的材料包括相同的元件。

公开(公告)号：US06635945B1

公开(公告)日：2003-10-21

申请号：US09580953

申请日：2000-05-30

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

IPC分类号： H01L2900

CPC分类号： H01L21/76232 ,  H01L29/0657

摘要： A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

摘要翻译： 描述半导体器件和形成器件的工艺。 该工艺包括在半导体衬底的电路形成侧上形成衬垫氧化膜; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化防止膜和焊盘氧化膜，从而暴露半导体衬底的表面; 使衬垫氧化膜水平地凹陷; 通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 以及氧化在半导体衬底中形成的沟槽。 所制造的器件具有圆形的上沟槽边缘，其通过对半导体衬底的暴露表面进行各向同性蚀刻并在沟槽氧化之前水平凹陷焊盘氧化膜而获得，由此仅需要一个氧化步骤。