公开(公告)号：US09515039B2

公开(公告)日：2016-12-06

申请号：US14983738

申请日：2015-12-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Lu-Yi Chen ,  Yu-Chuan Chen ,  Chang-Lun Lu

IPC: H05K1/00 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05567 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00014

Abstract: A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.

Abstract translation: 提供了一种衬底结构，其包括具有多个导电焊盘的衬底本体，以及设置在导电焊盘上的多个第一导电凸块和多个第二导电凸块。 每个第二导电凸块的宽度小于每个第一导电凸块，并且相对于基板主体的高度大于每个第一导电凸块相对于基板主体的高度。 因此，可以补偿回流处理后的第一预焊锡层和第二预焊锡层之间的高度差，因此第一导电凸块和第二导电凸块具有均匀的高度。

公开(公告)号：US09269602B2

公开(公告)日：2016-02-23

申请号：US13628582

申请日：2012-09-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/66

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/568 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

Abstract: A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield.

Abstract translation: 晶片级半导体封装的制造方法包括：在载体上形成具有暴露载体部分的第一开口的第一介电层; 在所述第一电介质层上形成电路层，所述电路层的一部分形成在所述第一开口中; 在所述第一电介质层和所述电路层上形成具有暴露所述电路层的部分的第二开口的第二电介质层; 在所述第二开口中形成导电凸块; 将半导体部件安装在导电凸块上; 形成用于封装半导体部件的密封剂; 并移除载体以露出电路层。 通过在安装半导体部件之前检测电路层的成品率，本发明避免与现有技术中发生的封装一起丢弃良好的半导体部件，从而节省制造成本并提高产品产量。

公开(公告)号：US11101235B2

公开(公告)日：2021-08-24

申请号：US16742040

申请日：2020-01-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L21/683 ,  H01L25/00 ,  H01L21/56 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H01L23/525 ,  H01L25/065 ,  H01L23/31

Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

公开(公告)号：US10403570B2

公开(公告)日：2019-09-03

申请号：US16157430

申请日：2018-10-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Hung-Yuan Li ,  Chieh-Lung Lai ,  Shih-Liang Peng ,  Chang-Lun Lu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US10128178B2

公开(公告)日：2018-11-13

申请号：US15258441

申请日：2016-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Hung-Yuan Li ,  Chieh-Lung Lai ,  Shih-Liang Peng ,  Chang-Lun Lu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US20170338173A1

公开(公告)日：2017-11-23

申请号：US15258441

申请日：2016-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Hung-Yuan Li ,  Chieh-Lung Lai ,  Shih-Liang Peng ,  Chang-Lun Lu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US20170033027A1

公开(公告)日：2017-02-02

申请号：US14982142

申请日：2015-12-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L23/498 ,  H01L23/373

CPC classification number: H01L21/6835 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/568 ,  H01L22/14 ,  H01L23/147 ,  H01L23/373 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2224/45099

Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.

Abstract translation: 提供了一种电子封装，包括：具有相对的第一和第二表面的电路结构，其中第一和第二电路层分别形成在电路结构的第一和第二表面上，第一电路层具有小于 第二电路层的; 形成在电路结构的第一表面上的分离层; 形成在所述分离层上并电连接到所述第一电路层的金属层; 电子元件，设置在电路结构的第一表面上并电连接到金属层; 以及形成在电路结构上以封装电子元件的密封剂。 通过将具有高I / O功能的电子元件设置在电路结构上，本发明消除了对具有芯层的封装基板的需要，从而减小了电子封装的厚度。

公开(公告)号：US20170005023A1

公开(公告)日：2017-01-05

申请号：US15008097

申请日：2016-01-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu

IPC: H01L23/31 ,  H01L21/66 ,  H01L21/56

CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00

Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.

Abstract translation: 提供电子封装，其包括：第一电路结构; 设置在所述第一电路结构的表面上的多个第一电子元件; 至少形成在所述第一电路结构的表面上的第一导电元件; 以及形成在第一电路结构的表面上并且封装第一电子元件和第一导电元件的第一密封剂，其中第一导电元件的一部分从第一密封剂暴露出来。 通过在电路结构上直接布置具有高I / O功能的电子元件，本公开不需要具有芯层的封装基板，从而减小电子封装的厚度。 本公开还提供了一种用于制造电子封装的方法。

公开(公告)号：US20150035164A1

公开(公告)日：2015-02-05

申请号：US14012447

申请日：2013-08-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

Abstract translation: 本发明提供一种半导体封装及其制造方法，包括：将具有相对的有源和非有源表面的半导体元件和邻接有源表面和非有效表面的侧表面放置在载体的沟槽中; 在所述凹槽中并且围绕所述半导体元件的侧表面的周边施加粘合剂材料; 在所述粘合剂材料和所述半导体元件的有源表面上形成介电层; 在所述电介质层上形成电连接到所述半导体元件的电路层; 以及在所述凹槽下方移除所述载体的第一部分，以将所述载体的第二部分保持在所述凹槽的侧壁上，以使所述第二部分用作支撑构件。 本发明不需要形成硅插入件，因此最终产品的总成本大大降低。

公开(公告)号：US10211082B2

公开(公告)日：2019-02-19

申请号：US15729842

申请日：2017-10-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu

IPC: H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/373 ,  H01L21/66 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/16 ,  H01L23/14

Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.