公开(公告)号：US11121028B2

公开(公告)日：2021-09-14

申请号：US16570325

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Ling-Fu Nieh ,  Pinlei Edmund Chu ,  Chi-Jen Liu ,  Yi-Sheng Lin ,  Ting-Hsun Chang ,  Chia-Wei Ho ,  Liang-Guang Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.

公开(公告)号：US20200006125A1

公开(公告)日：2020-01-02

申请号：US16570325

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.,

Inventor： Chun-Wei Hsu ,  Ling-Fu Nieh ,  Pinlei Edmund Chu ,  Chi-Jen Liu ,  Yi-Sheng Lin ,  Ting-Hsun Chang ,  Chia-Wei Ho ,  Liang-Guang Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.

公开(公告)号：US10515808B2

公开(公告)日：2019-12-24

申请号：US15267670

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Chi-Jen Liu ,  Ying-Liang Chuang ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Ming-Liang Yen

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/02 ,  H01L29/66 ,  B24B37/20 ,  H01L21/67

Abstract: A chemical mechanical polishing (CMP) system includes an O3/DIW generator, a polishing unit, and a cleaning unit. The O3/DIW generator is configured to generate an O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The polishing unit includes components for buffing a surface of a semiconductor structure, and a pipeline coupled to the O3/DIW generator to receive the O3/DIW solution for the buffing. The cleaning unit is coupled to the O3/DIW generator and is configured to clean the surface of the semiconductor structure using the O3/DIW solution.

公开(公告)号：US09917173B2

公开(公告)日：2018-03-13

申请号：US15407784

申请日：2017-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： Chi-Jen Liu ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Shich-Chang Suen

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.

公开(公告)号：US12297375B2

公开(公告)日：2025-05-13

申请号：US17141988

申请日：2021-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Chun-Wei Hsu ,  Li-Chieh Wu ,  Peng-Chung Jangjian ,  Kao-Feng Liao ,  Fu-Ming Huang ,  Wei-Wei Liang ,  Tang-Kuei Chang ,  Hui-Chi Huang

IPC: C09G1/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/535

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

公开(公告)号：US12131944B2

公开(公告)日：2024-10-29

申请号：US17460929

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Wei Hsu ,  Chih-Chieh Chang ,  Yi-Sheng Lin ,  Jian-Ci Lin ,  Jeng-Chi Lin ,  Ting-Hsun Chang ,  Liang-Guang Chen ,  Ji Cui ,  Kei-Wei Chen ,  Chi-Jen Liu

IPC: H01L21/768 ,  C09G1/02 ,  H01L23/522

CPC classification number: H01L21/7684 ,  C09G1/02 ,  H01L21/76877 ,  H01L23/5226

Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.

公开(公告)号：US12002684B2

公开(公告)日：2024-06-04

申请号：US18057728

申请日：2022-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC: H01L21/321 ,  B24B37/04 ,  B24B37/10 ,  C09G1/02

CPC classification number: H01L21/3212 ,  B24B37/044 ,  B24B37/107 ,  C09G1/02

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

公开(公告)号：US11996283B2

公开(公告)日：2024-05-28

申请号：US17874152

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/288 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/40114 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US20220359189A1

公开(公告)日：2022-11-10

申请号：US17874152

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US11133247B2

公开(公告)日：2021-09-28

申请号：US16525186

申请日：2019-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Ho ,  Chun-Wei Hsu ,  Chi-Hsiang Shen ,  Chi-Jen Liu ,  Yi-Sheng Lin ,  Yang-Chun Cheng ,  William Weilun Hong ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/321 ,  H01L23/00

Abstract: A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.