公开(公告)号：US10720406B2

公开(公告)日：2020-07-21

申请号：US16688905

申请日：2019-11-19

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Khoo Yien Sien

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L23/495 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

公开(公告)号：US09741643B2

公开(公告)日：2017-08-22

申请号：US15004208

申请日：2016-01-22

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49565 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

公开(公告)号：US20170213784A1

公开(公告)日：2017-07-27

申请号：US15004208

申请日：2016-01-22

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L23/49565 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

公开(公告)号：US08884414B2

公开(公告)日：2014-11-11

申请号：US13737697

申请日：2013-01-09

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Susan Goh Geok Ling ,  Ng Swee Tiang

IPC: H01L23/495 ,  H01L23/34 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/08245 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/73251 ,  H01L2224/80904 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/92222 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2924/00

Abstract: An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting therefrom and terminating substantially in the first plane; a top leadframe having a plurality of generally flat contact pads positioned substantially in a third plane above and parallel to the second plane and a plurality of leads having proximal end portions connected to the pad portions and having downwardly and outwardly extending distal end portions terminating substantially in said first plane; an IC die connected to the top leadframe, and the DAP; and encapsulation material encapsulating at least portions of the DAP, the lead bar, the top lead frame, and the IC die.

Abstract translation: 一种集成电路模块，包括基本上位于第一平面中的大致平坦的芯片附接焊盘（DAP）; 以及大致平坦的引线条，其基本上位于第二平面的上方并平行于所述第一平面，并且具有至少一个向下和向外延伸的引导杆引线，其从所述第一平面突出并基本上终止在所述第一平面内; 顶部引线框架具有多个基本上平坦的接触焊盘，其基本上位于第三平面中并且平行于第二平面，并且多个引线具有连接到焊盘部分的近端部分，并且具有向下和向外延伸的远端部分，其基本上终止于 第一架飞机 连接到顶部引线框架的IC管芯和DAP; 以及封装材料，其封装DAP，引线条，顶部引线框架和IC管芯的至少一部分。

公开(公告)号：US10515928B2

公开(公告)日：2019-12-24

申请号：US14167647

申请日：2014-01-29

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Khoo Yien Sien

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

公开(公告)号：US10115660B2

公开(公告)日：2018-10-30

申请号：US15688227

申请日：2017-08-28

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Wei Fen Sueann Lim

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

公开(公告)号：US20170110408A1

公开(公告)日：2017-04-20

申请号：US14887047

申请日：2015-10-19

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/538 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L21/768

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/0579 ,  H01L2224/05839 ,  H01L2224/08245 ,  H01L2224/29009 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2224/9222 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/35121 ,  H01L2924/3862 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2924/0781 ,  H01L2924/0665 ,  H01L2224/08 ,  H01L2224/80 ,  H01L2224/48

Abstract: An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.

公开(公告)号：US09275983B2

公开(公告)日：2016-03-01

申请号：US14706052

申请日：2015-05-07

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Yien Sien Khoo

IPC: H04L21/00 ,  H01L25/00 ,  H01L23/495 ,  H01L21/56 ,  H01L23/498 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/97 ,  H01L2924/12 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.

Abstract translation: 一种制造集成电路（IC）封装的方法，所述集成电路（IC）封装包括将裸片电连接和物理附接到插入器，将所述插入件附接到底部引线框架，将分立电路部件附接到所述插入器并将顶部引线框架附接到所述底部引线框架。

公开(公告)号：US20150214198A1

公开(公告)日：2015-07-30

申请号：US14167647

申请日：2014-01-29

Applicant: Texas Instruments Incorporated

Inventor： Han Meng Eugene Lee Lee ,  Anis Fauzi bin Abdul Aziz ,  Khoo Yien Sien

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L25/07 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

Abstract translation: 半导体系统（900）具有在第一平面中具有第一表面（401a）的平坦插入件（510），平行的第二平面中的第二表面（401b）和表面之间的均匀的第一高度（401）; 所述插入件在由间隙（412,415）分开的金属区域中被图案化，所述区域包括第一高度的金属和小于第一高度的第二高度（402）的金属; 绝缘材料填充第一和第二高度之间的间隙和区域差。 第一（610）和第二（611）组的半导体芯片具有连接到第一插入器表面的金属区域的第一端子，而第二组件的芯片的第二端子具有背离插入件的第二端子。 第一引线框架（700）附接到第二组芯片的第二端子，并且第二引线框架（800）附接到第二插入器表面的相应金属区域。

公开(公告)号：US20140191381A1

公开(公告)日：2014-07-10

申请号：US13737697

申请日：2013-01-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Susan Goh Geok Ling ,  Ng Swee Tiang

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/08245 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/73251 ,  H01L2224/80904 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/92222 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2924/00

Abstract: An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting therefrom and terminating substantially in the first plane; a top leadframe having a plurality of generally flat contact pads positioned substantially in a third plane above and parallel to the second plane and a plurality of leads having proximal end portions connected to the pad portions and having downwardly and outwardly extending distal end portions terminating substantially in said first plane; an IC die connected to the top leadframe, and the DAP; and encapsulation material encapsulating at least portions of the DAP, the lead bar, the top lead frame, and the IC die.

Abstract translation: 一种集成电路模块，包括基本上位于第一平面中的大致平坦的芯片附接焊盘（DAP）; 以及大致平坦的引线条，其基本上位于第二平面的上方并平行于所述第一平面，并且具有至少一个向下和向外延伸的引导杆引线，其从所述第一平面突出并终止于所述第一平面中; 顶部引线框架具有多个基本上平坦的接触焊盘，其基本上位于第三平面中并且平行于第二平面，并且多个引线具有连接到焊盘部分的近端部分，并且具有向下和向外延伸的远端部分，其基本上终止于 第一架飞机 连接到顶部引线框架的IC管芯和DAP; 以及封装材料，其封装DAP，引线条，顶部引线框架和IC管芯的至少一部分。