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    Technique for excess loop delay compensation in delta-sigma modulators
    12.
    发明授权
    Technique for excess loop delay compensation in delta-sigma modulators 有权
    Δ-Σ调制器中多余环路延迟补偿技术

    公开(公告)号：US09035813B2

    公开(公告)日：2015-05-19

    申请号：US14038350

    申请日：2013-09-26

    Applicant: Texas Instruments Incorporated

    Inventor： Eeshan Miglani

    IPC: H03M3/00

    CPC classification number: H03M3/39 ,  H03M3/30 ,  H03M3/37 ,  H03M3/424 ,  H03M3/464

    Abstract: A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog input signal and an output of a digital to analog converter. A comparator receives an output of the loop filter and generates a digital output signal. A reference select logic unit receives the digital output signal as a feedback and generates one or more switching signals. One or more switches are coupled to the comparator and each switch receives a pre-computed reference voltage. The one or more switches are activated by the one or more switching signals in response to the digital output signal.

    Abstract translation: 一种用于ΔΣ调制器中的过度环路延迟补偿的技术。 ΔΣ调制器包括环路滤波器。 环路滤波器接收模拟输入信号和数模转换器的输出。 比较器接收环路滤波器的输出并产生数字输出信号。 参考选择逻辑单元接收数字输出信号作为反馈并产生一个或多个切换信号。 一个或多个开关耦合到比较器，并且每个开关接收预先计算的参考电压。 响应于数字输出信号，一个或多个开关被一个或多个开关信号激活。

    FEEDFORWARD CANCELLATION OF POWER SUPPLY NOISE IN A VOLTAGE REGULATOR
    13.
    发明申请
    FEEDFORWARD CANCELLATION OF POWER SUPPLY NOISE IN A VOLTAGE REGULATOR 审中-公开
    电压调节器中电源噪声的取消

    公开(公告)号：US20150077070A1

    公开(公告)日：2015-03-19

    申请号：US14446815

    申请日：2014-07-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shuaeb Fazeel ,  Eeshan Miglani ,  Visvesvaraya Pentakota ,  Shagun Dusad

    IPC: G05F1/575

    CPC classification number: G05F1/575 ,  G05F1/467 ,  G05F3/222 ,  G05F3/242

    Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.

    Abstract translation: 公开了一种提供电源噪声前馈消除的电压调节器。 电压调节器包括接收电源电压并产生比例电压的过程跟踪电路。 跟踪电容器耦合到过程跟踪电路，并基于比例电压产生注入电压。 Ahuja补偿稳压器产生调节电压。 在Ahuja补偿调节器的反馈路径上提供注入电压。

    DC offset correction with low frequency signal support circuits and methods
    14.
    发明授权
    DC offset correction with low frequency signal support circuits and methods 有权
    直流偏移校正与低频信号支持电路和方法

    公开(公告)号：US08963607B1

    公开(公告)日：2015-02-24

    申请号：US14468009

    申请日：2014-08-25

    Applicant: Texas Instruments Incorporated

    Inventor： Sandeep Kesrimal Oswal ,  Eeshan Miglani ,  H. Mohammed Shuaeb Fazeel ,  Pradeep Nair ,  Anand Hariraj Udupa

    IPC: H03L5/00 ,  H03K5/003

    CPC classification number: H03K5/003

    Abstract: DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed.

    Abstract translation: DC偏移校正提供低频支持。 用于接收输入信号的第一输入端选择性地耦合到串联耦合在第一输入端和相应输出端之间的电阻和电容。 在校准阶段，串联电阻耦合在输入端和电容之间，输入的平均电压电平存储在电容上。 在信号处理阶段，当电阻被旁路时，充电的电容器串联在输入端子和输出端子之间。 获得的输出信号包含输入信号的高频和低频分量，输入信号中的直流偏移从输出信号中去除。 公开了一种差分电路和方法。 公开了另外的实施例。

    CALIBRATION SCHEME FOR A NON-LINEAR ADC
    16.
    发明申请
    CALIBRATION SCHEME FOR A NON-LINEAR ADC 有权

    公开(公告)号：US20220224349A1

    公开(公告)日：2022-07-14

    申请号：US17568972

    申请日：2022-01-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Himanshu Varshney ,  Viswanathan Nagarajan ,  Charls Babu ,  Narasimhan Rajagopal ,  Eeshan Miglani ,  Visvesvaraya A. Pentakota

    IPC: H03M1/10

    Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

    Sampling network with dynamic voltage detector for delay output
    17.
    发明授权
    Sampling network with dynamic voltage detector for delay output 有权

    公开(公告)号：US11309903B1

    公开(公告)日：2022-04-19

    申请号：US17131981

    申请日：2020-12-23

    Applicant: Texas Instruments Incorporated

    Inventor： Eeshan Miglani ,  Visvesvaraya Appala Pentakota ,  Jagannathan Venkataraman

    IPC: H03M1/56 ,  H03M1/06 ,  H03M1/50 ,  H03M1/38

    Abstract: A dynamic voltage-to-delay device may have voltage lines for receiving input signals during reset phases, and a current source, connected to the first and second voltage lines, for increasing voltages on the voltage lines during active phases. The voltage-to-delay device may also have comparators, connected to the voltage lines, for generating first and second output signals during the active phases when the voltages on the voltage lines reach a threshold voltage, such that a delay between the output signals is representative of a difference between voltages of the input signals. The voltage-to-delay device may have at least two current sources. The comparators may have a tail node to which a voltage is applied during a reset phase, and a current source for reducing the voltage at the tail node, and thereby reducing a threshold voltage during an active phase.

    Mixed signal circuit spur cancellation
    20.
    发明授权
    Mixed signal circuit spur cancellation 有权

    公开(公告)号：US10693444B1

    公开(公告)日：2020-06-23

    申请号：US16396873

    申请日：2019-04-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nagalinga Swamy Basayya Aremallapur ,  Eeshan Miglani ,  Visvesvaraya Pentakota ,  Praxal Sunilkumar Shah

    IPC: H03K3/013 ,  H03K3/037 ,  H03K21/10

    Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.

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