公开(公告)号：US09070785B1

公开(公告)日：2015-06-30

申请号：US14567507

申请日：2014-12-11

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Brian K. Kirkpatrick

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/32131 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

Abstract translation: 具有厚度大于4.85eV的功函数的厚TiN金属栅的集成电路，并具有工作功能小于4.25eV的薄TiN金属栅。 具有替代栅极PMOS TiN金属栅极晶体管的集成电路，其功函数大于4.85eV，并具有功函数小于4.25eV的替代栅极NMOS TiN金属栅极晶体管。 具有栅极第一PMOS TiN金属栅极晶体管的集成电路，其功函数大于4.85eV，并具有功函数小于4.25eV的栅极第一NMOS TiN金属栅极晶体管。

公开(公告)号：US20140124874A1

公开(公告)日：2014-05-08

申请号：US13671730

申请日：2012-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manoj Mehrotra ,  Hiroaki Niimi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

Abstract translation: 通过沿着形成的侧壁结构的内部形成高k栅极电介质来减小具有金属栅极和高k栅极电介质的MOS晶体管的栅极到源极和栅极到漏极的重叠电容 远离源头和排水沟。

公开(公告)号：US20210225711A1

公开(公告)日：2021-07-22

申请号：US17202978

申请日：2021-03-16

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L27/11 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US20190103321A1

公开(公告)日：2019-04-04

申请号：US16206045

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/11 ,  H01L21/02 ,  H01L29/20 ,  H01L29/16 ,  H01L27/092 ,  H01L29/10 ,  H01L29/161

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US20180130662A1

公开(公告)日：2018-05-10

申请号：US15865758

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  C23C16/455 ,  C23C16/458 ,  H01J37/32 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US20170133228A1

公开(公告)日：2017-05-11

申请号：US15404561

申请日：2017-01-12

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L21/67

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US09431509B2

公开(公告)日：2016-08-30

申请号：US14142323

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  James Joseph Chambers

IPC: H01L29/51 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier.

Abstract translation: 可以通过在高k栅介质层和PMOS晶体管的金属功函数层之间形成富氮钛基阻挡层来形成包含金属替换栅的集成电路。 富氮钛基阻挡层小于1纳米厚，钛与氮的原子比小于43:57。 可以通过在栅极电介质层上形成钛基层并随后将氮添加到钛基层来形成富氮钛基阻挡层。 在富氮钛基屏障上形成金属功函数层。

公开(公告)号：US20160204198A1

公开(公告)日：2016-07-14

申请号：US15079399

申请日：2016-03-24

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/16 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

公开(公告)号：US20150187903A1

公开(公告)日：2015-07-02

申请号：US14578722

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L29/49 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench

Abstract translation: 替代金属栅极晶体管结构和方法，其具有薄的氮化硅侧壁并且在替换栅极晶体管沟槽的垂直侧壁上具有很少或不具有高k电介质

公开(公告)号：US20150187773A1

公开(公告)日：2015-07-02

申请号：US14573021

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

Abstract translation: 包含n沟道finFET和p沟道finFET的集成电路在硅衬底上具有介电层。 finFET的鳍片具有比硅更高的迁移率的半导体材料。 n沟道finFET的鳍在通过衬底上的电介质层的第一沟槽中的第一硅 - 锗缓冲器上。 p沟道finFET的鳍在通过衬底上的电介质层的第二沟槽中的第二硅 - 锗缓冲器上。 翅片延伸至介电层上方至少10纳米。 散热片通过外延生长在电介质层的沟槽中的硅 - 锗缓冲器上形成，随后CMP平坦化到介电层。 电介质层凹入以暴露翅片。 翅片可以同时或分开地形成。