公开(公告)号：US20200273974A1

公开(公告)日：2020-08-27

申请号：US16802388

申请日：2020-02-26

Applicant: The Regents of the University of California

Inventor： Matthew Guidry ,  Stacia Keller ,  Umesh K. Mishra ,  Brian Romanczyk ,  Xun Zheng

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.

公开(公告)号：US09281183B2

公开(公告)日：2016-03-08

申请号：US14597989

申请日：2015-01-15

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L21/00 ,  H01L29/00 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  C30B25/02 ,  H01L29/20

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

Abstract translation: 一种制造III族氮化物半导体器件的方法，包括在氧化物生长和III族氮化物半导体的生长之间不暴露于空气中，依次生长III族氮化物半导体和氧化物以形成氧化物/ III族氮化物界面 。

公开(公告)号：US12230678B2

公开(公告)日：2025-02-18

申请号：US17291842

申请日：2019-11-07

Applicant: The Regents of the University of California

Inventor： Umesh K. Mishra ,  Stacia Keller ,  Elaheh Ahmadi ,  Chirag Gupta ,  Yusuke Tsukada

IPC: H01L29/20 ,  H01L27/092 ,  H01L29/205 ,  H01L29/737 ,  H01L29/778 ,  H01L29/78 ,  H01L33/32

Abstract: The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

公开(公告)号：US11594625B2

公开(公告)日：2023-02-28

申请号：US16802388

申请日：2020-02-26

Applicant: The Regents of the University of California

Inventor： Matthew Guidry ,  Stacia Keller ,  Umesh K. Mishra ,  Brian Romanczyk ,  Xun Zheng

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.

公开(公告)号：US11588096B2

公开(公告)日：2023-02-21

申请号：US16092165

申请日：2017-04-11

Applicant: The Regents of the University of California

Inventor： Yuuki Enatsu ,  Chirag Gupta ,  Stacia Keller ,  Umesh K. Mishra ,  Anchal Agarwal

IPC: H01L41/18 ,  H01L33/08 ,  H01L29/36 ,  H01L29/861 ,  H01L29/20 ,  H01L29/205 ,  H01L21/00 ,  H01L41/107 ,  H01L21/02

Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

公开(公告)号：US20220399475A1

公开(公告)日：2022-12-15

申请号：US17576716

申请日：2022-01-14

Applicant: The Regents of the University of California

Inventor： Kamruzzaman Khan ,  Elaheh Ahmadi ,  Stacia Keller ,  Christian Wurm ,  Umesh K. Mishra

IPC: H01L33/32 ,  H01L33/00

Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

公开(公告)号：US20190181329A1

公开(公告)日：2019-06-13

申请号：US16092165

申请日：2017-04-11

Applicant: The Regents of the University of California

Inventor： Yuuki Enatsu ,  Chirag Gupta ,  Stacia Keller ,  Umesh K. Mishra ,  Anchal Agarwal

IPC: H01L41/18 ,  H01L21/02 ,  H01L29/205 ,  H01L29/861 ,  H01L33/08 ,  H01L29/20 ,  H01L29/36

Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

公开(公告)号：US10312361B2

公开(公告)日：2019-06-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L29/51 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US09076927B2

公开(公告)日：2015-07-07

申请号：US14073698

申请日：2013-11-06

Applicant: The Regents of the University of California

Inventor： Stacia Keller ,  Carl J. Neufeld ,  Umesh K. Mishra ,  Steven P. DenBaars

IPC: H01L33/32 ,  H01L21/02 ,  H01L33/00 ,  H01L31/0735 ,  H01L31/18 ,  H01L33/12

CPC classification number: H01L33/32 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L31/0735 ,  H01L31/1856 ,  H01L33/007 ,  H01L33/12 ,  Y02E10/544

Abstract: A method of fabricating a heterostructure device, including (a) obtaining a first layer or substrate; (b) growing a second layer on the first layer or substrate; and (c) forming the second layer that is at least partially relaxed wherein (1) the first layer and the second layer have the same lattice structure but different lattice constants, (2) the first layer and the second layer form a heterojunction, and (3) the heterojunction forms an active area of a device or serves as a pseudo-substrate for the device.

Abstract translation: 一种制造异质结构器件的方法，包括（a）获得第一层或衬底; （b）在第一层或衬底上生长第二层; （c）形成至少部分松弛的第二层，其中（1）第一层和第二层具有相同的晶格结构但具有不同的晶格常数，（2）第一层和第二层形成异质结，以及 （3）异质结形成器件的有源区，或用作器件的伪衬底。

公开(公告)号：US08878249B2

公开(公告)日：2014-11-04

申请号：US13861808

申请日：2013-04-12

Applicant: The Regents of the University of California

Inventor： Jing Lu ,  Stacia Keller ,  Umesh K. Mishra

IPC: H01L29/66 ,  H01L21/338

CPC classification number: H01L29/778 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02581 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/8252 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method for growing high mobility, high charge Nitrogen polar (N-polar) or Nitrogen face (In,Al,Ga)N/GaN High Electron Mobility Transistors (HEMTs). The method can provide a successful approach to increase the breakdown voltage and reduce the gate leakage of the N-polar HEMTs, which has great potential to improve the N-polar or N-face HEMTs' high frequency and high power performance.

Abstract translation: 用于生长高迁移率，高电荷氮极（N极）或氮面（In，Al，Ga）N / GaN高电子迁移率晶体管（HEMT）的方法。 该方法可以提供成功的方法来增加击穿电压并降低N-极性HEMT的栅极泄漏，其具有改善N极或N面HEMTs高频和高功率性能的巨大潜力。