公开(公告)号：US20200273974A1

公开(公告)日：2020-08-27

申请号：US16802388

申请日：2020-02-26

Applicant: The Regents of the University of California

Inventor： Matthew Guidry ,  Stacia Keller ,  Umesh K. Mishra ,  Brian Romanczyk ,  Xun Zheng

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.

公开(公告)号：US20180013035A1

公开(公告)日：2018-01-11

申请号：US15698181

申请日：2017-09-07

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Robert M. Farrell, JR. ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

IPC: H01L33/16 ,  C30B23/02 ,  C30B25/18 ,  C30B29/40 ,  B82Y20/00 ,  H01L33/02 ,  H01L33/00 ,  H01S5/343 ,  H01L21/02 ,  H01S5/32 ,  H01S5/042 ,  H01S5/22

Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

公开(公告)号：US09793435B2

公开(公告)日：2017-10-17

申请号：US14953858

申请日：2015-11-30

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Robert M. Farrell, Jr. ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

IPC: H01L33/16 ,  H01L33/00 ,  B82Y20/00 ,  C30B23/02 ,  C30B25/18 ,  C30B29/40 ,  H01S5/343 ,  H01L33/02 ,  H01L21/02 ,  H01S5/042 ,  H01S5/22 ,  H01S5/32

CPC classification number: H01L33/16 ,  B82Y20/00 ,  C30B23/025 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L33/0004 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/02 ,  H01S5/0422 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/34333 ,  H01S2304/04

Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

公开(公告)号：US20160079738A1

公开(公告)日：2016-03-17

申请号：US14953858

申请日：2015-11-30

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Robert M. Farrell ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

IPC: H01S5/22 ,  H01S5/323 ,  H01S5/32

CPC classification number: H01L33/16 ,  B82Y20/00 ,  C30B23/025 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L33/0004 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/02 ,  H01S5/0422 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/34333 ,  H01S2304/04

Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Abstract translation: 一种用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的方法，包括鉴定特定器件应用的所需材料性质，基于所需材料性质选择半极性生长取向，选择 用于生长选择的半极性生长取向的合适底物，在衬底上生长平面半极性（Ga，Al，In，B）N模板或成核层，以及生长半极性（Ga，Al，In，B）N薄膜 ，平面半极性（Ga，Al，In，B）N模板或成核层上的异质结构或器件。 该方法导致大面积的半极性（Ga，Al，In，B）N薄膜，异质结构和器件平行于衬底表面。

公开(公告)号：US09281183B2

公开(公告)日：2016-03-08

申请号：US14597989

申请日：2015-01-15

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L21/00 ,  H01L29/00 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  C30B25/02 ,  H01L29/20

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

Abstract translation: 一种制造III族氮化物半导体器件的方法，包括在氧化物生长和III族氮化物半导体的生长之间不暴露于空气中，依次生长III族氮化物半导体和氧化物以形成氧化物/ III族氮化物界面 。

公开(公告)号：US20140211820A1

公开(公告)日：2014-07-31

申请号：US14229674

申请日：2014-03-28

Applicant: The Regents of the University of California

Inventor： Robert M. Farrell, JR. ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

IPC: H01S5/343

CPC classification number: H01L33/16 ,  B82Y20/00 ,  C30B23/025 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L33/0004 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/02 ,  H01S5/0422 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/34333 ,  H01S2304/04

Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Abstract translation: 一种用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的方法，包括鉴定特定器件应用的所需材料性质，基于所需材料性质选择半极性生长取向，选择 用于生长选择的半极性生长取向的合适底物，在衬底上生长平面半极性（Ga，Al，In，B）N模板或成核层，以及生长半极（Ga，Al，In，B）N薄膜 ，平面半极性（Ga，Al，In，B）N模板或成核层上的异质结构或器件。 该方法导致大面积的半极性（Ga，Al，In，B）N薄膜，异质结构和器件平行于衬底表面。

公开(公告)号：US20220102580A1

公开(公告)日：2022-03-31

申请号：US17422867

申请日：2020-01-16

Applicant: The Regents of the University of California

Inventor： Caroline E. Reilly ,  Umesh K. Mishra ,  Stacia Keller ,  Steven P. DenBaars

IPC: H01L33/00 ,  H01L31/18 ,  H01L33/02

Abstract: A method for fabricating a device, as well as the device itself, which includes growing a bonding layer on a first wafer or substrate, wherein the bonding layer includes at least partially relaxed features; and then bonding a second wafer or substrate to the features in on the first wafer or substrate, to cap and contact the features with separately grown material.

公开(公告)号：US20210399121A1

公开(公告)日：2021-12-23

申请号：US17353665

申请日：2021-06-21

Applicant: The Regents of the University of California

Inventor： Brian Romanczyk ,  Umesh K. Mishra ,  Pawana Shrestha ,  Matthew Guidry ,  James Buckwalter ,  Stacia Keller ,  Rohit Reddy Karnaty

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/267

Abstract: Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance.

公开(公告)号：US20210399096A1

公开(公告)日：2021-12-23

申请号：US17291842

申请日：2019-11-07

Applicant: The Regents of the University of California

Inventor： Umesh K. Mishra ,  Stacia Keller ,  Elaheh Ahmadi ,  Chirag Gupta ,  Yusuke Tsukada

IPC: H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/737 ,  H01L27/092 ,  H01L29/78 ,  H01L33/32

Abstract: Strain is used to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition.

公开(公告)号：US11101379B2

公开(公告)日：2021-08-24

申请号：US16461505

申请日：2017-11-16

Applicant: The Regents of the University of California

Inventor： Brian Romanczyk ,  Haoran Li ,  Elaheh Ahmadi ,  Steven Wienecke ,  Matthew Guidry ,  Xun Zheng ,  Stacia Keller ,  Umesh K. Mishra

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205

Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (tInGaN) and indium composition (xIn) was investigated for different channel thicknesses. With optimized tInGaN and xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm2/(V·s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In0.1Ga0.9N composite channel.