公开(公告)号：US11854800B2

公开(公告)日：2023-12-26

申请号：US17329477

申请日：2021-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/02321 ,  H01L21/02271 ,  H01L21/02345 ,  H01L21/02373 ,  H01L21/76224 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US20230386847A1

公开(公告)日：2023-11-30

申请号：US18358609

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L29/785 ,  H01L29/66477 ,  H01L21/2254 ,  H01L29/517 ,  H01L29/66545 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/513 ,  H01L29/41791

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US11776814B2

公开(公告)日：2023-10-03

申请号：US17201073

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L21/28185 ,  H01L21/2254 ,  H01L21/28176 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/41791 ,  H01L29/513

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US10950447B2

公开(公告)日：2021-03-16

申请号：US16907889

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US20200321216A1

公开(公告)日：2020-10-08

申请号：US16907889

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US12283622B2

公开(公告)日：2025-04-22

申请号：US18342146

申请日：2023-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Cheng-Po Chau ,  Yun Chen Teng

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/66

Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.

公开(公告)号：US12183581B2

公开(公告)日：2024-12-31

申请号：US18358609

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L21/225 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US12183573B2

公开(公告)日：2024-12-31

申请号：US18365517

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US20230386832A1

公开(公告)日：2023-11-30

申请号：US18365517

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/02321 ,  H01L29/66795 ,  H01L29/66545 ,  H01L21/02271 ,  H01L21/823481 ,  H01L21/76895 ,  H01L21/76883 ,  H01L21/76224 ,  H01L21/02345 ,  H01L21/02373

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US11444173B2

公开(公告)日：2022-09-13

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Jin-Mu Yin ,  Tsung-Chieh Hsiao ,  Chia-Lin Chuang ,  Li-Zhen Yu ,  Dian-Hau Chen ,  Shih-Wei Wang ,  De-Wei Yu ,  Chien-Hao Chen ,  Bo-Cyuan Lu ,  Jr-Hung Li ,  Chi-On Chui ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun-Cheng Chou ,  Ying-Liang Chuang ,  Yen-Chun Huang ,  Chih-Tang Peng ,  Cheng-Po Chau ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L29/45 ,  H01L29/08 ,  H01L29/165

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.