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    SHIELDING STRUCTURES
    12.
    发明申请
    SHIELDING STRUCTURES 有权

    公开(公告)号：US20220328440A1

    公开(公告)日：2022-10-13

    申请号：US17854840

    申请日：2022-06-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

    IPC: H01L23/00 ,  H01L21/48

    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

    Bump Integration with Redistribution Layer
    13.
    发明申请
    Bump Integration with Redistribution Layer 有权

    公开(公告)号：US20220246565A1

    公开(公告)日：2022-08-04

    申请号：US17492126

    申请日：2021-10-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ching-Wen Hsiao ,  Hong-Seng Shue ,  Ming-Da Cheng

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

    Shielding structures
    14.
    发明授权
    Shielding structures 有权

    公开(公告)号：US11380639B2

    公开(公告)日：2022-07-05

    申请号：US17114112

    申请日：2020-12-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

    IPC: H01L23/00 ,  H01L21/48

    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

    Shielding Structures
    16.
    发明申请
    Shielding Structures 审中-公开

    公开(公告)号：US20200168574A1

    公开(公告)日：2020-05-28

    申请号：US16392024

    申请日：2019-04-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

    IPC: H01L23/00 ,  H01L23/522

    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

    HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING
    17.
    发明申请
    HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING 有权
    通过TRENCH和EPITAXIAL DOPING进行高电压超级连接

    公开(公告)号：US20150061007A1

    公开(公告)日：2015-03-05

    申请号：US14011991

    申请日：2013-08-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-I Yang ,  Shou-Wei Lee ,  Shao-Chi Yu ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Po-Tao Chu

    IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/0634 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/308 ,  H01L21/324 ,  H01L21/761 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

    Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

    Abstract translation: 公开了一种高压超导装置。 该器件包括具有第一导电类型并且其中设置有相邻沟槽的半导体衬底区域。 相邻的沟槽各具有沟槽侧壁和沟槽底面。 具有第二导电类型的区域设置在沟槽中或与沟槽相邻并且在p-n结处与半导体衬底区域相遇。 栅极电极形成在半导体衬底区域上，并通过栅极电介质与半导体衬底区域电隔离。 具有第二导电类型的主体区域设置在靠近半导体衬底的表面的栅电极的相对侧上。 具有第一导电类型的源极区域设置在靠近半导体衬底的表面的栅电极的相对侧的体区内。

    Seal Ring Structure with Zigzag Patterns and Method Forming Same
    19.
    发明申请
    Seal Ring Structure with Zigzag Patterns and Method Forming Same 有权

    公开(公告)号：US20230066360A1

    公开(公告)日：2023-03-02

    申请号：US17659048

    申请日：2022-04-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Hung Chen ,  Hong-Seng Shue ,  Po-Hao Tsai ,  Mirng-Ji Lii

    IPC: H01L23/10 ,  H01L21/50 ,  H01L21/762 ,  H01L23/522

    Abstract: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

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