公开(公告)号：US11830742B2

公开(公告)日：2023-11-28

申请号：US17853600

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/3105 ,  H01L21/02362 ,  H01L21/02639 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/3245 ,  H01L21/32051 ,  H01L21/768 ,  H01L21/76262 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/76224

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US20230361039A1

公开(公告)日：2023-11-09

申请号：US18351957

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/8234 ,  H01L29/06 ,  H01L23/528 ,  H01L21/768 ,  H01L29/786 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/786

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ru

公开(公告)号：US11791206B2

公开(公告)日：2023-10-17

申请号：US16940247

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Pao-Sheng Chen ,  Pei-Hsuan Lee ,  Szu-Hua Wu ,  Chih-Chien Chi

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/02

CPC classification number: H01L21/76877 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/67028

Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.

公开(公告)号：US20190355694A1

公开(公告)日：2019-11-21

申请号：US16524146

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/66 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US09805951B1

公开(公告)日：2017-10-31

申请号：US15099779

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su

IPC: H01L21/44 ,  H01L21/321 ,  H01L21/288 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/02087 ,  H01L21/0273 ,  H01L21/2885 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate. The substrate has an edge region and a center region. The method also includes forming a dielectric ring in the edge region, forming a metal layer over the center region of the substrate and over the dielectric ring in the edge region of the substrate and polishing the metal layer in the center region and the edge region to expose the dielectric ring in the edge region of the substrate.

公开(公告)号：US20240379541A1

公开(公告)日：2024-11-14

申请号：US18784823

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Lee ,  Po-Hsiang Huang ,  Wen-Sheh Huang ,  Jen Hung Wang ,  Su-Jen Sung ,  Chih-Chien Chi ,  Pei-Hsuan Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

公开(公告)号：US20230121958A1

公开(公告)日：2023-04-20

申请号：US18068615

申请日：2022-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Lee ,  Po-Hsiang Huang ,  Wen-Sheh Huang ,  Jen Hung Wang ,  Su-Jen Sung ,  Chih-Chien Chi ,  Pei-Hsuan Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

公开(公告)号：US20220328309A1

公开(公告)日：2022-10-13

申请号：US17853600

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US20220293528A1

公开(公告)日：2022-09-15

申请号：US17242783

申请日：2021-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US11444002B2

公开(公告)日：2022-09-13

申请号：US16941541

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hsiao-Chung Liang ,  Hao-Yi Tsai ,  Chien-Ling Hwang ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Tin-Hao Kuo ,  Chih-Hsuan Tai

IPC: H01L23/40 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.