公开(公告)号：US20240250134A1

公开(公告)日：2024-07-25

申请号：US18313634

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Chun-Yuan Chen ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Kuo-Nan Yang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.

公开(公告)号：US10515944B2

公开(公告)日：2019-12-24

申请号：US16122762

申请日：2018-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan Chang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Sheng-Fong Chen ,  Po-Hsiang Huang ,  Hiranmay Biswas ,  Sheng-Hsiung Chen ,  Aftab Alam Khan

IPC: H01L29/06 ,  H01L27/02 ,  H01L23/522 ,  G06F17/50 ,  H01L27/118

Abstract: An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.

公开(公告)号：US20190006346A1

公开(公告)日：2019-01-03

申请号：US16125965

申请日：2018-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50

Abstract: A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.

公开(公告)号：US20170186691A1

公开(公告)日：2017-06-29

申请号：US15361970

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

IPC: H01L23/528 ,  G06F17/50 ,  H03K5/15

CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/62 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H03K5/15066

Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.

公开(公告)号：US09165882B2

公开(公告)日：2015-10-20

申请号：US14098435

申请日：2013-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Shen Lin ,  Jerry Chang-Jui Kao ,  Nitesh Katta ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Chi-Yeh Yu ,  Kuo-Nan Yang

IPC: G06F9/455 ,  G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  G06F2217/82 ,  H01L23/5226 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

Abstract translation: 公开了一种包括以下概述的操作的方法。 当金属片段的第一端和第二端周围的第一电流和第二电流的方向分别相反时，第一标准被确定为满足，其中金属片段是至少一个中的电源轨的一部分 半导体器件的设计文件，仅由两个端子通孔阵列封装。 当金属段的长度不大于电迁移临界长度时，确定满足第二标准。 当符合第一和第二标准时，金属段被包括在半导体器件中，具有取决于金属段的长度的第一电流密度极限。

公开(公告)号：US10964685B2

公开(公告)日：2021-03-30

申请号：US16724001

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan Chang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Sheng-Fong Chen ,  Po-Hsiang Huang ,  Hiranmay Biswas ,  Sheng-Hsiung Chen ,  Aftab Alam Khan

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

Abstract: An integrated circuit includes a cell layer, a first metal layer, a first conductive via, and a second conductive via. The cell layer includes first and second cells, in which the first cell is separated from the second cell by a non-zero distance. The first metal layer includes a first conductive feature and a second conductive feature, the first conductive feature overlaps the first cell and does not overlap the second cell, and the second conductive feature overlaps the second cell and does not overlap the first cell, in which the first conductive feature is aligned with the second conductive feature along lengthwise directions of the first and second conductive features. The first conductive via interconnects the cell layer and the first conductive feature of the first metal layer. The second conductive via interconnects the cell layer and the second conductive feature of the first metal layer.

公开(公告)号：US10956647B2

公开(公告)日：2021-03-23

申请号：US16214243

申请日：2018-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen Lin ,  Ming-Hsien Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/367

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

公开(公告)号：US10678990B2

公开(公告)日：2020-06-09

申请号：US16205441

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

IPC: G06F17/50 ,  G06F30/394 ,  H01L23/528 ,  G06F30/392 ,  G06F30/398 ,  G06F30/347 ,  G06F30/373 ,  H01L27/02 ,  G06F30/396 ,  G06F119/10 ,  G06F117/12

Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.

公开(公告)号：US20180060479A1

公开(公告)日：2018-03-01

申请号：US15250934

申请日：2016-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lo ,  Chin-Chou Liu ,  Kuo-Nan Yang ,  Yu-Jen Chang

IPC: G06F17/50 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/82 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14515 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/29099

Abstract: An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

公开(公告)号：US09405883B2

公开(公告)日：2016-08-02

申请号：US14857212

申请日：2015-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Shen Lin ,  Jerry Chang-Jui Kao ,  Nitesh Katta ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Chi-Yeh Yu ,  Kuo-Nan Yang

IPC: G06F17/50 ,  H01L23/522 ,  H01L23/528

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  G06F2217/82 ,  H01L23/5226 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.