利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.031 秒)

    Memory circuit improved in electrical characteristics
    12.
    发明授权
    Memory circuit improved in electrical characteristics 失效
    存储器电路改善了电气特性

    公开(公告)号：US5742551A

    公开(公告)日：1998-04-21

    申请号：US463851

    申请日：1995-06-05

    申请人： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    发明人： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    IPC分类号： H03F3/72 ,  H03K17/62 ,  G11C7/02

    CPC分类号： H03F3/72 ,  H03K17/6264 ,  H03F2203/7203

    摘要： A constant current source is connected in series to a current source circuit including a MOS transistor which is used as a current source for a differential output amplifier circuit, an emitter follower circuit or a source follower circuit used with a semiconductor integrated circuit. In a multiplex circuit, an input signal is inputted to each of base terminals of a plurality of bipolar transistors. When one input signal is selected, the bipolar transistor corresponding to the selected input signal is made to be operable with an input signal from a signal input terminal by a control circuit. The bipolar transistors corresponding to the non-selection input signals are turned OFF irrespective of potential levels of the individual input signals by current drawing circuits. There is also disclosed a semiconductor memory circuit having a plurality of memory cells, a memory cell selection scheme and a sense amplifier for amplifying data outputted from the selected memory cell, in which a constant current circuit is provided in series connection to the sense amplifier to enhance the performance characteristics of the memory circuit. Also, a plural memory array scheme is disclosed which employs multiplexing techniques connected to presense amplifier circuits of the respective memory arrays.

    摘要翻译： 恒流源串联连接到电流源电路，该电流源电路包括用作差分输出放大器电路的电流源的MOS晶体管，射极跟随器电路或与半导体集成电路一起使用的源极跟随器电路。 在复用电路中，输入信号被输入到多个双极晶体管的每个基极端子。 当选择一个输入信号时，与所选择的输入信号相对应的双极晶体管可以通过控制电路与来自信号输入端的输入信号一起工作。 对应于非选择输入信号的双极晶体管截止，而与当前绘图电路的各个输入信号的电位电平无关。 还公开了具有多个存储单元的半导体存储器电路，存储单元选择方案和用于放大从所选择的存储单元输出的数据的读出放大器，其中恒定电流电路与读出放大器串联连接， 提高存储电路的性能特点。 此外，公开了一种多重存储器阵列方案，其采用连接到相应存储器阵列的预放大器电路的复用技术。

    Image display
    15.
    发明申请
    Image display 有权
    图像显示

    公开(公告)号：US20050151729A1

    公开(公告)日：2005-07-14

    申请号：US11062824

    申请日：2005-02-23

    申请人： Hajime Akimoto ,  Mitsuru Hiraki ,  Hitoshi Nakahara ,  Takashi Akioka ,  Yoshiyuki Kaneko ,  Makoto Tsumura ,  Yoshiro Mikami

    发明人： Hajime Akimoto ,  Mitsuru Hiraki ,  Hitoshi Nakahara ,  Takashi Akioka ,  Yoshiyuki Kaneko ,  Makoto Tsumura ,  Yoshiro Mikami

    IPC分类号： G06F3/147 ,  G09G3/36

    CPC分类号： G06F3/147 ,  G09G3/3648 ,  G09G2300/0814 ,  G09G2310/04

    摘要： An image display displays image data on an image display part constructed by a display pixel array. In an image display in which image data input means for inputting image data so that the display pixel array has two neighboring areas having different frame rates (>0) is provided or image data is displayed on an image display part constructed by a display pixel array, there is provided image data input means which can input at least one moving image data and at least one still image data into the image display part at different frame rates (>0). A high precision image display can be realized hardly changing a display pixel rewriting speed. A moving image signal output circuit and a still image signal output circuit output image data to the display pixel array, and they are provided as circuit configurations independent of each other.

    摘要翻译： 图像显示器在由显示像素阵列构成的图像显示部分上显示图像数据。 在其中提供用于输入图像数据使得显示像素阵列具有两个具有不同帧速率（> 0）的相邻区域的图像数据输入装置的图像显示器中，或者在由显示像素阵列构成的图像显示部分上显示图像数据 提供了图像数据输入装置，其可以以不同的帧速率（> 0）将至少一个运动图像数据和至少一个静止图像数据输入图像显示部分。 可以实现几何改变显示像素重写速度的高精度图像显示。 运动图像信号输出电路和静止图像信号输出电路将图像数据输出到显示像素阵列，并且它们被提供为彼此独立的电路配置。

    Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device
    17.
    发明授权
    Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device 失效
    能够保持独立于外部时钟的脉冲宽度的信号的半导体器件和包括半导体器件的计算机系统

    公开(公告)号：US5920510A

    公开(公告)日：1999-07-06

    申请号：US934202

    申请日：1997-09-19

    申请人： Seigou Yukutake ,  Takashi Akioka ,  Kinya Mitsumoto ,  Takahiro Nagano ,  Hideo Maejima

    发明人： Seigou Yukutake ,  Takashi Akioka ,  Kinya Mitsumoto ,  Takahiro Nagano ,  Hideo Maejima

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C16/04

    CPC分类号： G11C7/1072 ,  G11C7/22 ,  G11C8/06

    摘要： A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.

    摘要翻译： 包含该半导体器件和计算机系统的半导体器件和计算机系统能够以与时钟信号的占空比无关地稳定地高速捕获外部信号。 外部信号ADD被电平锁存器捕获到地址锁存器22中。 电平锁存器在外部信号判定时刻的定时被控制为通过状态，并且在外部信号的判定周期中被控制为锁存状态。 脉冲发生电路通过芯片中的脉冲发生电路30控制将锁存器切换到通过状态到期望定时的定时。 根据上述结构，可以加速外部信号ADD的捕获，因为信号的捕获由设置时序确定。 此外，由于锁存周期由芯片中的脉冲发生电路控制，所以以稳定的方式执行操作，而不必依赖于外部时钟CLK的脉冲宽度。

    Constant voltage generation circuit
    18.
    发明授权
    Constant voltage generation circuit 失效
    恒压发电电路

    公开(公告)号：US5563502A

    公开(公告)日：1996-10-08

    申请号：US20809

    申请日：1993-02-22

    申请人： Takashi Akioka ,  Yutaka Kobayashi

    发明人： Takashi Akioka ,  Yutaka Kobayashi

    IPC分类号： G05F3/30 ,  G05F3/26 ,  G05F3/16 ,  G05F3/20

    CPC分类号： G05F3/267

    摘要： A circuit for generating a constant voltage, free of dependence on temperature changes, by adding a voltage having positive temperature dependence to a voltage having negative temperature dependence. A current generation circuit for generating a current having positive temperature dependence is connected with an element for converting this current to a voltage by way of a proportional current supply circuit, for example, a current mirror circuit.

    摘要翻译： 通过向具有负温度依赖性的电压添加具有正温度依赖性的电压，产生不依赖于温度变化的恒定电压的电路。 用于产生具有正温度依赖性的电流的电流产生电路与用于通过比例电流供应电路（例如电流镜电路）将该电流转换为电压的元件连接。

    Multiplex circuit arrangement for use with a semiconductor integrated circuit
    19.
    发明授权
    Multiplex circuit arrangement for use with a semiconductor integrated circuit 失效
    用于半导体集成电路的多路电路装置

    公开(公告)号：US5523713A

    公开(公告)日：1996-06-04

    申请号：US464344

    申请日：1995-06-05

    申请人： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    发明人： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    IPC分类号： H03F3/72 ,  H03K17/62

    CPC分类号： H03F3/72 ,  H03K17/6264 ,  H03F2203/7203

    摘要： A multiplex circuit is disclosed in which a plurality of bipolar transistors are combined and in which the respective base terminals thereof are used as inputs, thereby to construct an emitter follower type multiplex circuit. In such an emitter follower type multiplex circuit, the multiplexing function of non-selection/selection is effected by controlling the base potential of the respective bipolar transistors by providing a MOS transistor between each base and a high potential of the power source through a resistor and a current drawing circuit. In accordance with such a scheme, when a selection of one input signal is made, the bipolar transistor corresponding thereto is permitted to turn ON on the basis of an input signal supplied to the base terminal thereof. The bipolar transistors corresponding to the non-selection input signals are maintained OFF, through activating the current drawing circuits associated therewith, irrespective of the potential levels of the incoming input signals supplied to the base terminals thereof. In the emitter follower type multiplex circuit, a constant current source is also provided between the commonly connected emitters of the bipolar transistors and the power source of low potential. The multiplex arrangement effected can be of the collector dot type multiplex circuit. Such multiplex circuits are used with a semiconductor integrated circuit such as a memory circuit.

    摘要翻译： 公开了一种多路复用电路，其中组合了多个双极晶体管，并且将其各自的基极端子用作输入，从而构成射极跟随器型多路复用电路。 在这种射极跟踪器型多路复用电路中，通过在每个基极之间设置MOS晶体管和通过电阻器的电源的高电位之间来控制各个双极型晶体管的基极电位来实现非选择/选择的多路复用功能， 电流绘制电路。 根据这种方案，当进行一个输入信号的选择时，与其相对应的双极晶体管被允许基于提供给其基极的输入信号而导通。 与非选择输入信号相对应的双极晶体管通过激活与其相关的电流绘制电路而保持关闭，而不管提供给其基极的输入信号的电位电平如何。 在射极跟踪器型多路复用电路中，在双极晶体管的共同连接的发射极和低电位的电源之间也设置恒流源。 所实现的复用布置可以是集电极点型多路复用电路。 这种多路复用电路与诸如存储电路的半导体集成电路一起使用。