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11.发明授权公开(公告)号：US07811904B2
公开(公告)日：2010-10-12
申请号：US11701561
申请日：2007-01-31
申请人： Tao Feng , Ming Sun , Yueh-Se Ho , Kai Liu
发明人： Tao Feng , Ming Sun , Yueh-Se Ho , Kai Liu
IPC分类号： H01L21/00
CPC分类号： H01L21/67132 , H01L21/288 , H01L21/6836 , H01L24/02 , H01L24/11 , H01L2221/68327 , H01L2224/0401 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014
摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.
摘要翻译： 公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。 该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形 保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取 从保护胶带上取下模具。
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公开(公告)号：US20080207094A1
公开(公告)日：2008-08-28
申请号：US11712846
申请日：2007-02-28
CPC分类号： B24B7/228 , B24B41/06 , B28D5/0011 , B28D5/0052 , H01L24/06 , H01L24/73 , H01L2224/0401 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/06181 , H01L2224/16225 , H01L2224/94 , H01L2924/00014 , H01L2224/05599 , H01L2224/03 , H01L2224/0555 , H01L2224/0556
摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.
摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。
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公开(公告)号：US08361903B2
公开(公告)日：2013-01-29
申请号：US12753426
申请日：2010-04-02
IPC分类号： H01L21/302
CPC分类号： B24B7/228 , B24B41/06 , B28D5/0011 , B28D5/0052 , H01L24/06 , H01L24/73 , H01L2224/0401 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/06181 , H01L2224/16225 , H01L2224/94 , H01L2924/00014 , H01L2224/05599 , H01L2224/03 , H01L2224/0555 , H01L2224/0556
摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.
摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。
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公开(公告)号：US20100221431A1
公开(公告)日：2010-09-02
申请号：US12753426
申请日：2010-04-02
CPC分类号： B24B7/228 , B24B41/06 , B28D5/0011 , B28D5/0052 , H01L24/06 , H01L24/73 , H01L2224/0401 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/06181 , H01L2224/16225 , H01L2224/94 , H01L2924/00014 , H01L2224/05599 , H01L2224/03 , H01L2224/0555 , H01L2224/0556
摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.
摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。
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公开(公告)号：US07776746B2
公开(公告)日：2010-08-17
申请号：US11712846
申请日：2007-02-28
IPC分类号： H01L21/302
CPC分类号： B24B7/228 , B24B41/06 , B28D5/0011 , B28D5/0052 , H01L24/06 , H01L24/73 , H01L2224/0401 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/06181 , H01L2224/16225 , H01L2224/94 , H01L2924/00014 , H01L2224/05599 , H01L2224/03 , H01L2224/0555 , H01L2224/0556
摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.
摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。
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公开(公告)号：US08716063B2
公开(公告)日：2014-05-06
申请号：US13007356
申请日：2011-01-14
申请人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/00
CPC分类号： H01L29/7827 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/81 , H01L29/0657 , H01L29/41741 , H01L29/4175 , H01L29/45 , H01L29/49 , H01L29/7802 , H01L2224/02371 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要翻译： 封装了功率晶圆级芯片级封装（CSP）和制造工艺。 功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。
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公开(公告)号：US20140076846A1
公开(公告)日：2014-03-20
申请号：US13621289
申请日：2012-09-16
IPC分类号： B32B38/00
CPC分类号： B32B38/0012 , B32B2038/0016 , B32B2038/0092 , B32B2309/10 , B32B2457/14 , H01L21/67132 , H01L21/6836 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834 , H01L2224/0345 , H01L2224/0401 , H01L2224/0556 , H01L2224/05568 , H01L2224/06183 , H01L2224/131 , H01L2224/16105 , H01L2224/16238 , H01L2224/17051 , H01L2224/17104 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/00014 , H01L2924/00012 , H01L2224/03 , H01L2924/014 , H01L2224/05552
摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.
摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。
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公开(公告)号：US08426960B2
公开(公告)日：2013-04-23
申请号：US11963690
申请日：2007-12-21
申请人： Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
发明人： Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
IPC分类号： H01L23/48
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/02 , H01L24/11 , H01L24/17 , H01L2221/68354 , H01L2224/0231 , H01L2224/0233 , H01L2224/0239 , H01L2224/0401 , H01L2224/04042 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.
摘要翻译： 公开了一种用于在晶片级芯片级封装工艺中进行背对背电连接的方法。 将包含多个半导体芯片的晶片安装在封装基板上。 多个半导体芯片包括暴露背面的一个或多个电极。 去除晶片上的两个或更多个相邻芯片之间的划痕线以形成较宽的间隙。 将导电材料施加到半导体芯片的背面和间隙中。 然后通过在两个或更多个芯片的背侧和侧壁上留下导电材料来切割两个或更多个芯片之间的间隙中的导电材料。 结果，导电材料提供从芯片的背面上的电极到芯片的前侧的电连接。
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公开(公告)号：US08217748B2
公开(公告)日：2012-07-10
申请号：US12397473
申请日：2009-03-04
申请人： Tao Feng , Xiaotian Zhang , François Hébert , Ming Sun
发明人： Tao Feng , Xiaotian Zhang , François Hébert , Ming Sun
CPC分类号： H01L23/495 , H01F3/14 , H01F17/0033 , H01F17/062 , H01F27/2828 , H01F2027/2814 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , Y10T29/49073 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： An inductive power electronics package is disclosed. It has a circuit substrate with power inductor attached atop. The power inductor has inductor core of closed magnetic loop with an interior window. The closed magnetic loop can include air gap for inductance adjustment. The circuit substrate has bottom half-coil forming elements constituting a bottom half-coil beneath the inductor core. Also provided are top half-coil forming elements interconnected with the bottom half-coil forming elements to form an inductive coil enclosing the inductor core. An inner connection chip can be added in the interior window for interconnecting bottom half-coil forming elements with top half-coil forming elements. An outer connection chip can be added about the inductor core for interconnecting bottom half-coil forming elements with top half-coil forming elements outside the inductor core. A power Integrated Circuit can be attached to the top side of the circuit substrate as well.
摘要翻译： 公开了感应电力电子封装。 它有一个电路基板，带有功率电感器。 功率电感器具有具有内部窗口的闭合磁环的电感器芯。 封闭的磁环可以包括用于电感调节的气隙。 电路基板具有构成电感器芯下方的下半线圈的底部半线圈形成元件。 还提供了与底部半线圈形成元件互连以形成包围电感器芯的感应线圈的顶部半线圈形成元件。 内部连接芯片可以添加到内部窗口中，用于将底部半线圈形成元件与顶部半线圈形成元件相互连接。 外部连接芯片可以围绕电感器芯添加，用于将底部半线圈形成元件与电感器芯外部的顶部半线圈形成元件互连。 功率集成电路也可以连接到电路基板的顶侧。
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20.发明申请WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET'S) 审中-公开金属氧化物半导体场效应晶体管（MOSFET）的等离子切割尺寸包装公开(公告)号：US20120202320A1
公开(公告)日：2012-08-09
申请号：US13452750
申请日：2012-04-20
IPC分类号： H01L21/78
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05124 , H01L2224/05155 , H01L2224/05568 , H01L2224/05644 , H01L2224/11334 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/13091 , H01L2924/00014 , H01L2924/013
摘要： Wafer-level chip scale packaging of metal-oxide-semiconductor-field-effect-transistors (MOSFET's) provides protection and good solder-ability to a die backside by fabricating a plurality of power MOSFET devices with die contacts on a wafer that can later be cut into individual die. A plurality of contact pads is included on the wafer to provide connectivity to the die contacts. A layer which includes aluminum (Al) or zinc (Zn) is electrolessly plated on a backside of the wafer to form a metalized backside. The plating tank used in this step is not contaminated. The contact pads and metalized backside are plated with a layer of electroless nickel (Ni) followed by a layer of gold (Au). Solder balls are formed on each of the contact pads after their plating with nickel (Ni) and gold (Au). The wafer is diced to yield MOSFET wafer level chip-scale packages which provide protection and good solder-ability to the die backside.
摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）的晶片级芯片尺寸封装通过在晶片上制造具有芯片触点的多个功率MOSFET器件来提供对模具背面的保护和良好的焊接能力，其可以稍后 切成个人死亡 多个接触焊盘包括在晶片上以提供与管芯触点的连接。 将包含铝（Al）或锌（Zn）的层无电镀在晶片的背面以形成金属化的背面。 本步骤中使用的镀槽不会受到污染。 接触垫和金属化背面镀有一层无电镀镍（Ni），然后镀一层金（Au）。 在镀镍（Ni）和金（Au）之后，在每个接触焊盘上形成焊球。 切割晶圆以产生MOSFET晶片级芯片级封装，为模具背面提供保护和良好的焊接能力。
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