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    AIR GAP FORMATION AND INTEGRATION USING A PATTERNING CAP
    13.
    发明申请
    AIR GAP FORMATION AND INTEGRATION USING A PATTERNING CAP 有权
    空气隙形成和整合使用图案盖

    公开(公告)号：US20090309230A1

    公开(公告)日：2009-12-17

    申请号：US12336884

    申请日：2008-12-17

    申请人： ZHENJIANG CUI ,  Mehul Naik ,  Christopher D. Bencher ,  Kenneth MacWilliams

    发明人： ZHENJIANG CUI ,  Mehul Naik ,  Christopher D. Bencher ,  Kenneth MacWilliams

    IPC分类号： H01L21/768 ,  H01L23/535

    CPC分类号： H01L23/5222 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap.

    摘要翻译： 膜图案及其结果的方法。 在一个实施方案中，在诸如镶嵌层的基底上形成无定形碳掩模。 在无定形碳掩模上沉积间隔层，并且蚀刻间隔层以形成间隔物并暴露无定形碳掩模。 无定形碳掩模被选择性地去除到间隔物以暴露衬底层。 间隔填充层沉积在间隔物周围以覆盖基底层，但暴露间隔物。 选择性地移除间隔物以在衬底上形成间隙填充掩模。 间隙填充掩模的图案在一个实施方式中转移到镶嵌层中以去除IMD的至少一部分并形成气隙。

    Dielectric materials to prevent photoresist poisoning
    14.
    发明申请
    Dielectric materials to prevent photoresist poisoning 失效
    介电材料防止光致抗蚀剂中毒

    公开(公告)号：US20050014361A1

    公开(公告)日：2005-01-20

    申请号：US10847891

    申请日：2004-05-18

    申请人： Son Nguyen ,  Michael Armacost ,  Mehul Naik ,  Girish Dixit ,  Ellie Yieh

    发明人： Son Nguyen ,  Michael Armacost ,  Mehul Naik ,  Girish Dixit ,  Ellie Yieh

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76808

    摘要： Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.

    摘要翻译： 提供了用于沉积电介质材料的方法，用作防蚀涂层和牺牲电介质材料在镶嵌形成中。 在一个方面，提供了一种处理衬底的方法，包括通过使含氧有机硅化合物和酸性化合物反应，在酸性电介质层上沉积光致抗蚀剂材料，并使光致抗蚀剂层图形化，在衬底上沉积酸性介电层。 通过蚀刻部分特征定义，沉积酸性电介质材料，蚀刻特征定义的其余部分，然后除去酸性介电材料以形成特征定义，可以将酸性介电层用作形成特征定义的牺牲层。

    Dual damascene fabrication with low k materials
    17.
    发明授权
    Dual damascene fabrication with low k materials 失效
    具有低k材料的双镶嵌制造

    公开(公告)号：US07618889B2

    公开(公告)日：2009-11-17

    申请号：US11488529

    申请日：2006-07-18

    申请人： Mehul Naik

    发明人： Mehul Naik

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76834 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76808 ,  H01L21/76835

    摘要： The invention provides methods and apparatuses for fabricating a dual damascene structure on a substrate. First, trench lithography and trench patterning are performed on the surface of a substrate to etch a low-k dielectric material layer to a desired etch depth to form a trench prior to forming of a via. The trenches can be filled with an organic fill material and a dielectric hard mask layer can be deposited. Then, via lithography and via resist pattering are performed. Thereafter, the dielectric hard mask and the organic fill material are sequentially etched to form vias on the surface of the substrate, where the trenches are protected by the organic fill material from being etched. A bottom etch stop layer on the bottom of the vias is then etched and the organic fill material is striped. As a result, the invention provides good patterned profiles of the via and trench openings of a dual damascene structure.

    摘要翻译： 本发明提供了在衬底上制造双镶嵌结构的方法和装置。 首先，在衬底的表面上进行沟槽光刻和沟槽图案化以将低k电介质材料层蚀刻到期望的蚀刻深度，以在形成通孔之前形成沟槽。 可以用有机填充材料填充沟槽，并且可以沉积电介质硬掩模层。 然后，通过光刻和通孔抗蚀剂图案进行。 此后，依次蚀刻电介质硬掩模和有机填充材料，以在衬底的表面上形成通孔，其中沟槽被有机填充材料保护而不被蚀刻。 然后蚀刻通孔底部的底部蚀刻停止层，并将有机填充材料条纹化。 结果，本发明提供了双镶嵌结构的通孔和沟槽开口的良好的图案轮廓。

    Etch depth control for dual damascene fabrication process
    18.
    发明授权
    Etch depth control for dual damascene fabrication process 失效
    蚀刻深度控制双镶嵌工艺

    公开(公告)号：US07572734B2

    公开(公告)日：2009-08-11

    申请号：US11877964

    申请日：2007-10-24

    申请人： Mehul Naik ,  Suketu A. Parikh ,  Michael D. Armacost

    发明人： Mehul Naik ,  Suketu A. Parikh ,  Michael D. Armacost

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31116 ,  H01J37/32091 ,  H01J37/3266 ,  H01J2237/3347 ,  H01L21/76807 ,  H01L21/76808 ,  H01L22/26

    摘要： The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.

    摘要翻译： 电介质膜堆叠中的双镶嵌结构的沟槽过孔蚀刻中的蚀刻深度被控制为在基底的致密区域和开放区域上相同，并且解决微加载问题。 沟槽蚀刻工艺适于包括使用两个蚀刻化学物质的正向微加载蚀刻工艺和反向微加载蚀刻工艺，以及在沉积介电膜堆叠期间包含掺杂剂材料层或有机填充材料层 。 在一个实施例中，一旦在掺杂剂材料层的预定位置处达到电介质膜堆叠的蚀刻，则在通孔上的沟槽的蚀刻从正向微负载切换到反向微负载。 在另一个实施例中，有机沟槽填充材料层的蚀刻在反向微加载过程中进行，然后在正向微加载过程中蚀刻介电膜堆叠。

    PLASMA SURFACE TREATMENT TO PREVENT PATTERN COLLAPSE IN IMMERSION LITHOGRAPHY
    19.
    发明申请
    PLASMA SURFACE TREATMENT TO PREVENT PATTERN COLLAPSE IN IMMERSION LITHOGRAPHY 审中-公开
    等离子体表面处理，以防止浸渍图中的图案褶皱

    公开(公告)号：US20090104541A1

    公开(公告)日：2009-04-23

    申请号：US11877559

    申请日：2007-10-23

    申请人： Eui Kyoon Kim ,  Deenesh Padhi ,  Huixiong Dai ,  Mehul Naik ,  Martin Jay Seamons ,  Bok Hoen Kim

    发明人： Eui Kyoon Kim ,  Deenesh Padhi ,  Huixiong Dai ,  Mehul Naik ,  Martin Jay Seamons ,  Bok Hoen Kim

    IPC分类号： G03F1/00

    CPC分类号： G03F7/091 ,  G03F7/11

    摘要： The present invention comprises a method of reducing photoresist mask collapse when the photoresist mask is dried after immersion development. As feature sizes continue to shrink, the capillary force of water used to rinse a photoresist mask approaches the point of being greater than adhesion force of the photoresist to the ARC. When the capillary force exceeds the adhesion force, the features of the mask may collapse because the water pulls adjacent features together as the water dries. By depositing a hermetic oxide layer over the ARC before depositing the photoresist, the adhesion force may exceed the capillary force and the features of the photoresist mask may not collapse.

    摘要翻译： 本发明包括当浸渍显影后干燥光致抗蚀剂掩模时减少光致抗蚀剂掩模塌陷的方法。 随着特征尺寸的不断缩小，用于冲洗光致抗蚀剂掩模的水的毛细管力接近光致抗蚀剂对ARC的粘附力。 当毛细管力超过粘附力时，面具的特征可能会因为水干燥而将相邻的特征拉到一起而崩溃。 通过在沉积光致抗蚀剂之前在ARC上沉积气密的氧化物层，粘合力可能会超过毛细管力，并且光致抗蚀剂掩模的特征可能不会崩溃。

    METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY
    20.
    发明申请
    METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY 有权
    用于减少RC延迟的电介质层中产生气泡的方法和装置

    公开(公告)号：US20090093112A1

    公开(公告)日：2009-04-09

    申请号：US11869396

    申请日：2007-10-09

    申请人： AMIR AL-BAYATI ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang 'David' Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

    发明人： AMIR AL-BAYATI ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang 'David' Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.

    摘要翻译： 一种用于在互连结构的电介质材料中产生气隙的方法和装置。 一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层， 在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分 在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。