公开(公告)号：US10211096B1

公开(公告)日：2019-02-19

申请号：US15928492

申请日：2018-03-22

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Abbas Ali ,  Yaping Chen ,  Chao Zuo ,  Seetharaman Sridhar ,  Yunlong Liu

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L23/532

Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

公开(公告)号：US09825030B2

公开(公告)日：2017-11-21

申请号：US15255311

申请日：2016-09-02

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L27/108 ,  H01L27/088 ,  H01L29/423 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28 ,  H01L29/66 ,  H01L29/94 ,  H01L23/528 ,  H01L29/49 ,  H01L21/265

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

公开(公告)号：US20160315155A1

公开(公告)日：2016-10-27

申请号：US15188188

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Zachary K. Lee ,  Yufei Xiong ,  Yunlong Liu ,  Wei Tang

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7834

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

Abstract translation: 一种制造FET的方法包括在衬底的表面上形成栅极。 沟槽接触部在位于基板表面附近的第一区域和位于第一区域下方的第二区域之间形成。 衬底的表面涂覆有导电材料，其中导电材料至少部分地覆盖栅极并对沟槽接触线进行导线以电连接第一区域和第二区域。 在沟槽接触处留下空隙。 介电材料被施加到导电材料上，其中电介质材料至少部分地填充沟槽接触中的空隙。 导电材料的至少一部分从栅极被蚀刻。

公开(公告)号：US09406774B1

公开(公告)日：2016-08-02

申请号：US14692337

申请日：2015-04-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Zachary K. Lee ,  Yufei Xiong ,  Yunlong Liu ,  Wei Tang

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7834

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

Abstract translation: 一种制造FET的方法包括在衬底的表面上形成栅极。 沟槽接触部在位于基板表面附近的第一区域和位于第一区域下方的第二区域之间形成。 衬底的表面涂覆有导电材料，其中导电材料至少部分地覆盖栅极并对沟槽接触线进行导线以电连接第一区域和第二区域。 在沟槽接触处留下空隙。 介电材料被施加到导电材料上，其中电介质材料至少部分地填充沟槽接触中的空隙。 导电材料的至少一部分从栅极被蚀刻。

公开(公告)号：US11417736B2

公开(公告)日：2022-08-16

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

公开(公告)号：US11322594B2

公开(公告)日：2022-05-03

申请号：US17134706

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Fei Ma ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Baoqiang Niu ,  Rui Liu ,  Zhi Peng Feng ,  Seetharaman Sridhar ,  Sunglyong Kim

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/765 ,  H01L29/423 ,  H01L27/24 ,  H01L21/8234

Abstract: A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.

公开(公告)号：US09991350B2

公开(公告)日：2018-06-05

申请号：US15188110

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Yufei Xiong ,  Yunlong Liu ,  Zachary K. Lee ,  Peng Hu

IPC: H01L23/48 ,  H01L29/417 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L21/288 ,  H01L21/285 ,  H01L29/08 ,  H01L29/423 ,  H01L23/485 ,  H01L23/535 ,  H01L21/74 ,  H01L29/06 ,  H01L29/45 ,  H01L29/10

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

公开(公告)号：US20160329423A1

公开(公告)日：2016-11-10

申请号：US15049209

申请日：2016-02-22

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hong Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66734

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Abstract translation: 半导体器件包含垂直MOS晶体管，其沟槽中的沟槽栅极延伸穿过垂直漂移区到漏极区。 这些沟槽在门下有现场板; 场板与漂移区相邻并且具有多个段。 将场板与漂移区分离的沟槽中的电介质衬垫的厚度大于门和主体之间的栅极电介质层。 电介质衬垫在沟槽底部的场板的下段上比在栅极正下方的上段更厚。 沟槽栅极可以与场板电隔离，或者可以连接到上部段。 场板的段可以彼此电隔离或者可以在沟槽中彼此连接。

公开(公告)号：US09461131B1

公开(公告)日：2016-10-04

申请号：US14739230

申请日：2015-06-15

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L21/336 ,  H01L27/108 ,  H01L29/423 ,  H01L27/088 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract translation: 一种集成电路，其包括在衬底中的沟槽，其具有在沟槽的侧壁和底部上生长的高质量沟槽氧化物，其中形成在侧壁上的高质量沟槽氧化物的厚度与形成在底部上的厚度之比较小 超过1.2。 包括具有高质量氧化物的沟槽的集成电路通过首先在1050℃至1250℃的温度范围内在稀释氧中生长牺牲氧化物而形成，剥离牺牲氧化物，在稀释氧中生长高质量的氧化物 在1050℃至1250℃的温度下加入反式1,2-二氯乙烯，并在1050℃至1250℃的温度范围内在惰性环境中退火高品质氧化物。

公开(公告)号：US09455222B1

公开(公告)日：2016-09-27

申请号：US14974834

申请日：2015-12-18

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Hong Yang ,  Eugen Pompiliu Mindricelu ,  Robert Graham Shaw

IPC: H01L23/62 ,  H01L23/525 ,  H01L27/06 ,  H01L23/532 ,  H03F3/45

CPC classification number: H01L23/5256

Abstract: A fuse circuit includes a substrate, a top semiconductor layer doped a first conductivity type having a well doped a second conductivity type formed therein including a well contact. A field dielectric layer (FOX) is on the semiconductor layer. A fuse is on the FOX within the well including a fuse body including electrically conductive material having a first and second fuse contact. A transistor is formed in the semiconductor layer including a control terminal (CT) with CT contact, a first terminal (FT) with FT contact, and a second terminal (ST) with a ST contact. A coupling path is between the CT contact and well contact, a first resistor is coupled between the FT contact and CT contact, and a coupling path is between the ST contact and the first fuse contact.

Abstract translation: 熔丝电路包括衬底，掺杂有第一导电类型的顶部半导体层，其具有在其中形成的良好掺杂的第二导电类型，其包括阱接触。 场致电介质层（FOX）位于半导体层上。 保险丝位于阱内的FOX上，包括一个保险丝体，包括具有第一和第二保险丝接触的导电材料。 在包括具有CT接触的控制端子（CT），具有FT接触的第一端子（FT）和具有ST触点的第二端子（ST）的半导体层中形成晶体管。 耦合路径在CT触点和阱接触之间，第一电阻耦合在FT触点和CT触点之间，耦合路径位于ST触点和第一熔丝触点之间。