公开(公告)号：US09496388B2

公开(公告)日：2016-11-15

申请号：US15069089

申请日：2016-03-14

Applicant: Texas Instruments Incorporated

Inventor： Thomas Eugene Grebs ,  Touhidur Rahman ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/861 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/861

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Abstract translation: 沟槽MOSFET器件包括第一掺杂类型的半导体层。 MOS晶体管单元处于半导体层中的第二掺杂类型的体区。 晶体管单元包括第一单元类型，包括提供第一栅电极的第一沟槽或者第一栅电极位于第一沟槽和第二沟槽之间的半导体表面上，并且第一源区形成在体区中。 第一栅电极与第一源区电隔离。 第二单元类型具有提供第二栅电极的第三沟槽，或者第二栅极位于第三沟槽和第四沟槽之间的半导体表面上，第二源极区在体区中。 导电构件将第二栅极电极，第一源极区域和第二源极区域直接连接在一起。

公开(公告)号：US20160197178A1

公开(公告)日：2016-07-07

申请号：US15069089

申请日：2016-03-14

Applicant: Texas Instruments Incorporated

Inventor： Thomas Eugene Grebs ,  Touhidur Rahman ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/861

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

公开(公告)号：US20160197177A1

公开(公告)日：2016-07-07

申请号：US15069038

申请日：2016-03-14

Applicant: Texas Instruments Incorporated

Inventor： Thomas Eugene Grebs ,  Touhidur Rahman ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/861

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Abstract translation: 沟槽MOSFET器件包括第一掺杂类型的半导体层。 MOS晶体管单元处于半导体层中的第二掺杂类型的体区。 晶体管单元包括第一单元类型，包括提供第一栅电极的第一沟槽或者第一栅电极位于第一沟槽和第二沟槽之间的半导体表面上，并且第一源区形成在体区中。 第一栅电极与第一源区电隔离。 第二单元类型具有提供第二栅电极的第三沟槽，或者第二栅极位于第三沟槽和第四沟槽之间的半导体表面上，第二源极区在体区中。 导电构件将第二栅极电极，第一源极区域和第二源极区域直接连接在一起。

公开(公告)号：US20160133616A1

公开(公告)日：2016-05-12

申请号：US14737072

申请日：2015-06-11

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/042 ,  H01L31/0216 ,  H01L25/00 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L31/028 ,  H01L27/082

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Abstract translation: 一种自供电的电子系统包括：嵌入第二芯片（302）中的单晶半导体的第一芯片（401），该第二芯片形成为与脊状接合的容器。 组装的芯片被嵌套，并形成电子器件，该电子器件依次组装在由p型掺杂的低级硅片形成的平板中，该片状物作为与脊（331）相邻的容器（330）。 板坯的平坦侧面（335）包括形成具有p型体积的pn结（315）的大量n掺杂区域（314）。 通过p型脊（331）的金属填充的深硅通孔（350）将p区域作为阳极将n区与作为阳极的阳极的脊表面上的端子（322）连接。 pn结上的电压用作器件的电源。

公开(公告)号：US10153220B2

公开(公告)日：2018-12-11

申请号：US15785778

申请日：2017-10-17

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L23/057 ,  H01L23/08 ,  H01L25/16 ,  H01L25/04 ,  H01L21/48 ,  H01L25/00 ,  H01L21/78 ,  H01L23/13

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

公开(公告)号：US10109614B2

公开(公告)日：2018-10-23

申请号：US15053089

申请日：2016-02-25

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/065 ,  H01L23/06 ,  H01L25/18 ,  H01L25/00 ,  H01L23/053 ,  H01L23/00 ,  H01L21/50 ,  H01L23/13 ,  H01L23/14 ,  H01L29/06 ,  H01L23/498

Abstract: An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.

公开(公告)号：US20180096978A1

公开(公告)日：2018-04-05

申请号：US15820246

申请日：2017-11-21

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L25/00 ,  H01L27/088 ,  H01L27/082 ,  H01L31/18 ,  H01L31/042 ,  H01L31/028 ,  H01L31/0216 ,  H01L31/02

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20180040527A1

公开(公告)日：2018-02-08

申请号：US15785778

申请日：2017-10-17

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L21/48 ,  H01L25/16 ,  H01L25/00 ,  H01L21/78 ,  H01L23/13

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/78 ,  H01L23/057 ,  H01L23/08 ,  H01L23/13 ,  H01L25/16 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (I-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

公开(公告)号：US09640519B2

公开(公告)日：2017-05-02

申请号：US14737072

申请日：2015-06-11

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/028 ,  H01L31/042 ,  H01L31/0216 ,  H01L27/082 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L25/00 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L29/06 ,  H01L23/498

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20160133535A1

公开(公告)日：2016-05-12

申请号：US14702031

申请日：2015-05-01

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L21/78 ,  H01L25/00 ,  H01L25/16 ,  H01L21/48

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/78 ,  H01L23/057 ,  H01L23/08 ,  H01L23/13 ,  H01L25/16 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

Abstract translation: 封装的电子系统包括构造成脊（114）的低等级硅（lg-Si）的板状物（210），其构成包括适于容纳半导体芯片和嵌入式电气部件的凹陷中心区域的深度凹陷（112）， 深度至少等于芯片和部件的厚度，由连接到中心区域中的附接垫的系统端子（209b）覆盖的脊; 和具有厚度的半导体芯片（120,130），并且在相对的芯片侧的至少一个上具有端子，所述芯片端子附接到中心区域端子，使得相对的芯片侧与板条脊上的系统端子共面。