公开(公告)号：US08294219B2

公开(公告)日：2012-10-23

申请号：US12179538

申请日：2008-07-24

Applicant: Sandra G. Malhotra ,  Pragati Kumar ,  Sean Barstow ,  Tony Chiang ,  Prashant B. Phatak ,  Wen Wu ,  Sunil Shanker

Inventor： Sandra G. Malhotra ,  Pragati Kumar ,  Sean Barstow ,  Tony Chiang ,  Prashant B. Phatak ,  Wen Wu ,  Sunil Shanker

IPC: H01L21/02

CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。

公开(公告)号：US08278735B2

公开(公告)日：2012-10-02

申请号：US12901239

申请日：2010-10-08

Applicant: Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

Inventor： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: H01L21/02

CPC classification number: H01L28/40 ,  C23C14/083 ,  C23C14/3464 ,  C23C16/405 ,  C23C16/45531 ,  H01L21/02186 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02266 ,  H01L21/0228

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US08278215B2

公开(公告)日：2012-10-02

申请号：US13098926

申请日：2011-05-02

Applicant: Zhi-Wen Sun ,  Bob Kong ,  Igor Ivanov ,  Tony Chiang

Inventor： Zhi-Wen Sun ,  Bob Kong ,  Igor Ivanov ,  Tony Chiang

IPC: H01L21/44

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76879 ,  H01L31/022425 ,  H01L31/18 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y02E10/50

Abstract: Processes for minimizing contact resistance when using nickel silicide (NiSi) and other similar contact materials are described. These processes include optimizing silicide surface cleaning, silicide surface passivation against oxidation and techniques for diffusion barrier/catalyst layer deposition. Additionally, processes for generating a noble metal (for example platinum, iridium, rhenium, ruthenium, and alloys thereof) activation layer that enables the electroless barrier layer deposition on a NiSi-based contact material are described. The processes may be employed when using NiSi-based materials in other end products. The processes may be employed on silicon-based materials.

Abstract translation: 描述了当使用硅化镍（NiSi）和其他类似的接触材料时使接触电阻最小化的方法。 这些方法包括优化硅化物表面清洗，硅化物表面钝化与氧化以及用于扩散阻挡层/催化剂层沉积的技术。 另外，描述了能够在NiSi基接触材料上产生无电极阻挡层沉积的贵金属（例如铂，铱，铼，钌及其合金）活化层的方法。 当在其它最终产品中使用NiSi基材料时，可以采用这些方法。 该方法可以用于硅基材料。

公开(公告)号：US08274066B2

公开(公告)日：2012-09-25

申请号：US13252360

申请日：2011-10-04

Applicant: Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

Inventor： Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

IPC: H01L47/00

CPC classification number: H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元结构的方法。 通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。 例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。 在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

公开(公告)号：US20120100723A1

公开(公告)日：2012-04-26

申请号：US13337728

申请日：2011-12-27

Applicant: Sunil Shanker ,  Tony Chiang

Inventor： Sunil Shanker ,  Tony Chiang

IPC: H01L21/31

CPC classification number: C23C16/047 ,  C23C16/04 ,  C23C16/45536 ,  C23C16/45551 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/45591 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/50 ,  C23C16/5096 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32366

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

公开(公告)号：US08143164B2

公开(公告)日：2012-03-27

申请号：US12368110

申请日：2009-02-09

Applicant: Bob Kong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Jinhong Tong ,  Tony Chiang

Inventor： Bob Kong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Jinhong Tong ,  Tony Chiang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/02068 ,  C23C18/1651 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76852 ,  H01L21/76874

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.

Abstract translation: 本发明的实施方案描述了处理半导体衬底的方法，其包括将锌化溶液施加到半导体衬底上以在含钛层上形成锌钝化层，所述锌化溶液包含锌盐FeCl 3和pH调节剂。

公开(公告)号：US08129288B2

公开(公告)日：2012-03-06

申请号：US12433842

申请日：2009-04-30

Applicant: Sunil Shanker ,  Tony Chiang

Inventor： Sunil Shanker ,  Tony Chiang

IPC: H01L21/31

CPC classification number: C23C16/047 ,  C23C16/04 ,  C23C16/45536 ,  C23C16/45551 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/45591 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/50 ,  C23C16/5096 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32366

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract translation: 描述组合等离子体增强沉积技术，包括指定衬底的多个区域，为多个区域的至少第一区域提供前体，以及向第一区域提供等离子体，以将第一材料沉积在使用 第一前体，其中所述第一材料不同于形成在所述基底的第二区域上的第二材料。

公开(公告)号：US20120044751A1

公开(公告)日：2012-02-23

申请号：US13286472

申请日：2011-11-01

Applicant: Yun Wang ,  Prashant Phatak ,  Tony Chiang

Inventor： Yun Wang ,  Prashant Phatak ,  Tony Chiang

IPC: G11C11/36

CPC classification number: G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.

Abstract translation: 根据各种实施例，使用双极开关的电阻式开关存储器元件和存储元件阵列包括仅包括不是齐纳二极管的单个二极管的选择元件。 即使当在二极管的反向偏置方向上施加小于二极管的击穿电压的开关电压时，本文所述的电阻式开关存储元件也可以切换。 存储器元件能够在瞬态脉冲电压对存储元件可见时的非常短的时间内进行切换，因此每个存储器单元可以使用单个二极管。

公开(公告)号：US08053364B2

公开(公告)日：2011-11-08

申请号：US12243322

申请日：2008-10-01

Applicant: Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

Inventor： Wayne French ,  Pragati Kumar ,  Prashant Phatak ,  Tony Chiang

IPC: H01L21/44 ,  C23C14/00

CPC classification number: C23C14/083 ,  C23C14/0042 ,  C23C14/54 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元的方法。 经验数据可用于产生与金属 - 绝缘体 - 金属结构的金属氧化物沉积相关联的滞后曲线，曲线测量反映了在使用偏置目标的溅射过程期间所使用的阴极电压的期望电特性的变化 。 通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。 对于一组给定的材料（例如金属和氧源），可以制造这样的电池的多电平存储器单元或阵列，以便具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff） 或“关”电流与“关”电流（Ion / Ioff）的最大比例。

公开(公告)号：US20110248264A1

公开(公告)日：2011-10-13

申请号：US12905945

申请日：2010-10-15

Applicant: Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

Inventor： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

IPC: H01L29/66

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。