公开(公告)号：US20070176658A1

公开(公告)日：2007-08-02

申请号：US11698892

申请日：2007-01-29

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H03L7/00

CPC classification number: H03L7/0814 ,  H03K5/133 ,  H03K5/135 ,  H03K5/26 ,  H03K2005/00071 ,  H03L7/07 ,  H03L7/087 ,  H03L7/091

Abstract: Three flip-flops receive a common data signal input through a data terminal based on different timing signals which are obtained from an external timing signal and differ from one another by a specific delay step. A judging circuit judges whether or not the output data of the three flip-flops coincide with one another. If all the output data coincide with one another, the latch timing is maintained, whereas if the output data of the flip-flop latching the data signal at a fastest or latest timing differs from the output data of the flip-flop latching the data signal at the central timing, the judging circuit changes the variable timing to obtain a suitable latch timing.

Abstract translation: 三个触发器基于从外部定时信号获得的不同的定时信号，通过数据终端接收公共数据信号，并且通过特定的延迟步骤彼此不同。 判断电路判断三个触发器的输出数据是否彼此一致。 如果所有输出数据彼此一致，则保持锁存定时，而如果在最快或最新的定时锁存数据信号的触发器的输出数据不同于触发器的输出数据锁存数据信号 在中央定时，判断电路改变可变定时以获得合适的锁定定时。

公开(公告)号：US07095599B2

公开(公告)日：2006-08-22

申请号：US10759250

申请日：2004-01-20

Applicant: Noriyuki Maekawa ,  Motoyuki Abe ,  Makoto Yamakado ,  Toru Ishikawa ,  Kooji Shibata

Inventor： Noriyuki Maekawa ,  Motoyuki Abe ,  Makoto Yamakado ,  Toru Ishikawa ,  Kooji Shibata

IPC: H01H47/00 ,  H01H47/28 ,  H01H47/32

CPC classification number: F02D41/20 ,  F02D2041/2079 ,  F02D2200/503

Abstract: When voltage changes occur in the battery used as a power supply in a fuel injection system, the amount of fuel injection also changes and the required amount of fuel injected cannot be obtained. To eliminate this problem, a fuel injector system is provided which has a fuel injection valve with at least one coil, a power supply, a power supply voltage detector, and a control unit for controlling the fuel injection valve. The control unit sets a reference value of a power supply voltages, and the above-mentioned fuel injection valve is controlled so as to obtain the required ampere-turns by reducing the resultant inductance of the coil when a power supply voltage detection value is less than the above-mentioned reference value, and the resultant inductance of the coil is increased when the power voltage detection value is greater than the reference value.

Abstract translation: 当在用作燃料喷射系统中的电源的电池中发生电压变化时，燃料喷射量也改变，并且不能获得所需的燃料量。 为了消除这个问题，提供一种燃料喷射器系统，其具有至少一个线圈的燃料喷射阀，电源，电源电压检测器和用于控制燃料喷射阀的控制单元。 控制单元设定电源电压的基准值，并且控制上述燃料喷射阀，以便当电源电压检测值小于时，通过减小线圈的合成电感来获得所需的安培匝数 当电源电压检测值大于参考值时，上述参考值和线圈的合成电感增加。

公开(公告)号：US06970028B2

公开(公告)日：2005-11-29

申请号：US10785015

申请日：2004-02-25

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/081 ,  H03L7/06

CPC classification number: H03L7/0814

Abstract: DLL circuit with a small minimum delay time while allowing a wide range of adjustment of the delay time. The DLL circuit according includes a first delay circuit for delaying an input clock signal (CLK1) to output a plurality of delayed clock signals (T1 to TN), a first selector (7) for selecting a first delayed clock signal (CLK_E) and a second delayed clock signal (CLK_O) from among the plurality of delayed clock signals (T1 to TN), for output, a second delay circuit (3) for delaying the input clock signal (CLK1) to generate a slightly delayed clock signal (CLKD), a second selector (4) for selecting two selected clock signals (FDLE, FDLO) from among the slightly delayed clock signal (CLKD), first delayed clock signal (CLK_E), and second delayed clock signal (CLK_O), and a delay synthesis circuit (5) for generating an internal clock signal (CLKIN) from the selected clock signals (FDLE, FDLO), for output.

Abstract translation: DLL电路具有较小的最小延迟时间，同时允许宽范围的延时调整。 所述DLL电路包括用于延迟输入时钟信号（CLK1）以输出多个延迟的时钟信号（T 1>到T N N）的第一延迟电路， 第一选择器（7），用于从多个延迟时钟信号（T 1至T N N）中选择第一延迟时钟信号（CLK_E）和第二延迟时钟信号（CLK_O） 用于输出用于延迟输入时钟信号（CLK 1）以产生稍微延迟的时钟信号（CLKD）的第二延迟电路（3）;第二选择器（4），用于选择两个选择的时钟信号（FDLE， （CLKD），第一延迟时钟信号（CLK_E）和第二延迟时钟信号（CLK_O）的延迟合成电路（5），以及用于产生内部时钟信号（CLK < ）从所选择的时钟信号（FDLE，FDLO）中输出。

公开(公告)号：US5748018A

公开(公告)日：1998-05-05

申请号：US790800

申请日：1997-01-30

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H03K19/0175 ,  G06F1/12 ,  H04L7/00 ,  H04L7/02 ,  H04L25/40 ,  H03L7/00

CPC classification number: H03K3/00 ,  H04L7/0008 ,  H04L7/02

Abstract: In a data transfer system for use in an integrated circuit, a data output circuit comprises a D-FF for latching data to be transferred, in synchronism with an external clock signal, an output buffer receiving and outputting the data latched in the D-FF, and another output buffer receiving the external clock signal for outputting a delayed clock signal which is delayed from the external clock signal by a delay amount of the D-FF. On the other hand, a data input circuit including a first D-FF for receiving the data to be transferred outputted from the D-FF of the data output circuit, in synchronism with the delayed clock signal supplied from the D-FF of the data output circuit, and a second D-FF for fetching the data received in the first D-FF, in synchronism with the external clock signal.

Abstract translation: 在用于集成电路的数据传输系统中，数据输出电路包括用于与外部时钟信号同步地锁存要传送的数据的D-FF，输出缓冲器，其接收并输出在D-FF中锁存的数据 以及接收外部时钟信号的另一个输出缓冲器，用于输出从外部时钟信号延迟D-FF的延迟量的延迟时钟信号。 另一方面，一种数据输入电路，包括用于从数据输出电路的D-FF输出的要被传送的数据的第一D-FF与从数据的D-FF提供的延迟的时钟信号同步 输出电路，以及与外部时钟信号同步地提取在第一D-FF中接收的数据的第二D-FF。

公开(公告)号：US5691673A

公开(公告)日：1997-11-25

申请号：US665757

申请日：1996-06-17

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H01L25/00 ,  H01L23/66 ,  H01P1/00 ,  H01P3/08 ,  H01P5/00

CPC classification number: H01L24/06 ,  H01L23/66 ,  H01L24/49 ,  H01L2223/6655 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111

Abstract: In a semiconductor integrated circuit apparatus, a semiconductor chip (device, or module) has input/output portions each connected to two external pins (or terminals). The two external pins are connected to an incoming transmission line and an outgoing transmission line, respectively. The following formula is satisfied: ##EQU1## where Z is an impedance of each of the transmission lines; L1 and L2 are inductances of the two pins; and C1 is a capacitance of each of the input/output portions.

Abstract translation: 在半导体集成电路装置中，半导体芯片（器件或模块）具有各自连接到两个外部引脚（或端子）的输入/输出部分。 两个外部引脚分别连接到输入传输线和输出传输线。 满足以下公式：其中Z是每个传输线的阻抗; L1和L2是两个引脚的电感; 并且C1是每个输入/输出部分的电容。

公开(公告)号：US5521870A

公开(公告)日：1996-05-28

申请号：US354086

申请日：1994-12-06

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: G01R31/28 ,  G11C7/10 ,  G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G11C29/32 ,  G11C29/34 ,  G11C29/38 ,  G11C11/40

CPC classification number: G11C7/1036 ,  G11C29/32 ,  G11C29/38 ,  G11C2029/4002

Abstract: A semiconductor memory device includes a plurality of memory blocks, a write circuit for writing data into the memory blocks, a read circuit for reading data from the memory blocks, a plurality of serial registers, each of which is connected to the corresponding memory block to output serially a plurality of data read from the memory block, a plurality of switches, each of which is arranged between two adjacent ones of the serial registers to connect the serial registers in series, and a coincidence detection circuit for detecting a coincidence of data outputted from a final serial register arranged at a final end of the serial registers connected by the switches with data outputted from a serial register arranged immediately before the final serial register.

Abstract translation: 半导体存储器件包括多个存储块，用于将数据写入存储块的写入电路，用于从存储块读取数据的读取电路，多个串行寄存器，每个串行寄存器连接到相应的存储器块 输出从存储块读取的多个数据，多个开关，每个开关布置在串联寄存器的两个相邻串行寄存器之间，以串联串行寄存器;以及一致检测电路，用于检测输出的数据的一致 从布置在由开关连接的串行寄存器的最后一端的最终串行寄存器与从紧接在最后串行寄存器之前排列的串行寄存器输出的数据组成。

公开(公告)号：US5463452A

公开(公告)日：1995-10-31

申请号：US195049

申请日：1994-02-14

Applicant: Shigeru Inaba ,  Masaaki Fukuhara ,  Makoto Hirota ,  Mitsuo Yamamoto ,  Jun Abe ,  Hideaki Miyata ,  Takayuki Sunaga ,  Toru Ishikawa ,  Yoshio Shiina ,  Toru Isosu ,  Makoto Kanno

Inventor： Shigeru Inaba ,  Masaaki Fukuhara ,  Makoto Hirota ,  Mitsuo Yamamoto ,  Jun Abe ,  Hideaki Miyata ,  Takayuki Sunaga ,  Toru Ishikawa ,  Yoshio Shiina ,  Toru Isosu ,  Makoto Kanno

IPC: G03G15/08 ,  G03G15/06 ,  G03G15/09 ,  G03G21/00

CPC classification number: G03G15/065 ,  G03G15/0907

Abstract: A single-component developing apparatus comprising a developer holding member having a peripheral surface, a power supply section applying an AC developing bias voltage to the developer holding member, the AC developing bias voltage having a waveform with predetermined minimum value, maximum value and period, an electrostatic latent image receiving member opposing the developer holding member across a gap having predetermined width, a developer supplying section supplying a developer to the developer holding member, and a developer regulating member forming developer into a thin layer on the peripheral surface of the developer holding member by pressing on the developer holding member.In this arrangement the developer holding member transports the thin layer of developer towards the electrostatic latent image receiving member, and the transported thin layer of developer flies from the developer holding member across the gap to the electrostatic latent image receiving member in accordance with the AC developing bias voltage. The waveform of the AC developing bias voltage satisfies the inequality:t.sub.A /T.ltoreq.0.4wherein t.sub.A is rise time from minimum value to maximum value, and T is the period.

Abstract translation: 一种单组分显影装置，包括具有外围表面的显影剂保持构件，向显影剂保持构件施加AC显影偏压的电源部分，具有预定最小值，最大值和周期的波形的AC显影偏压， 静电潜像接收部件，其跨越具有预定宽度的间隙与显影剂保持部件相对;将显影剂供给到显影剂保持部件的显影剂供给部;以及将显影剂调整部件形成为显影剂保持部件的外周面上的薄层 通过按压显影剂保持构件。 在这种布置中，显影剂保持构件将薄的显影剂传送到静电潜像接收构件，并且所输送的显影剂薄层根据AC显影剂从显影剂保持构件跨越间隙飞往静电潜像接收构件 偏压。 AC显影偏压的波形满足不等式：tA / T

公开(公告)号：US5416790A

公开(公告)日：1995-05-16

申请号：US147779

申请日：1993-11-04

Applicant: Keiichi Yodoshi ,  Akira Ibaraki ,  Masayuki Shono ,  Shoji Honda ,  Takatoshi Ikegami ,  Nobuhiko Hayashi ,  Koutarou Furusawa ,  Atushi Tajiri ,  Toru Ishikawa ,  Kenichi Matsukawa ,  Teruaki Miyake ,  Takenori Goto ,  Mitsuaki Matsumoto ,  Daisuke Ide ,  Yasuyuki Bessho

Inventor： Keiichi Yodoshi ,  Akira Ibaraki ,  Masayuki Shono ,  Shoji Honda ,  Takatoshi Ikegami ,  Nobuhiko Hayashi ,  Koutarou Furusawa ,  Atushi Tajiri ,  Toru Ishikawa ,  Kenichi Matsukawa ,  Teruaki Miyake ,  Takenori Goto ,  Mitsuaki Matsumoto ,  Daisuke Ide ,  Yasuyuki Bessho

IPC: H01S5/065 ,  H01S5/20 ,  H01S5/223 ,  H01S5/32 ,  H01S3/19

CPC classification number: H01S5/20 ,  H01S5/2231 ,  H01S5/0658 ,  H01S5/2004 ,  H01S5/3211

Abstract: A semiconductor laser with a self-sustained pulsation is disclosed in which a first cladding layer of first conductive type, an active layer and a second cladding layer of second conductive type having a striped ridge are formed in that order on a semiconductor substrate of first conductive type. The first and second cladding layers have a refractive index smaller than and a band gap larger than the active layer. A saturable optical absorbing layer having a band gap of energy substantially equal to the energy corresponding to lasing wavelength is formed in both the first and second cladding layers. Further, a barrier layer having a refractive index smaller than and a band gap larger than the first and second cladding layers is formed between the first cladding layer and the active layer and/or between the active layer and the second cladding layer.

Abstract translation: 公开了一种具有自持脉动的半导体激光器，其中在第一导电半导体衬底上依次形成第一导电类型，有源层和具有条纹脊的第二导电类型的第二包层的第一包层 类型。 第一和第二覆层具有比有源层更大的折射率和更大的带隙。 在第一和第二包层中均形成有具有基本上等于与激发波长相对应的能量的能隙带的饱和光吸收层。 此外，在第一包层和有源层之间和/或有源层和第二包层之间形成折射率小于第一和第二包层的折射率的带隙的阻挡层。

公开(公告)号：US5020066A

公开(公告)日：1991-05-28

申请号：US457256

申请日：1989-12-27

Applicant: Kenichi Iga ,  Akira Ibaraki ,  Kenji Kawashima ,  Kotaro Furusawa ,  Toru Ishikawa

Inventor： Kenichi Iga ,  Akira Ibaraki ,  Kenji Kawashima ,  Kotaro Furusawa ,  Toru Ishikawa

IPC: H01S5/00 ,  H01S5/042 ,  H01S5/183

CPC classification number: H01S5/18308 ,  H01S5/0207 ,  H01S5/02461 ,  H01S5/18305 ,  H01S5/18361 ,  H01S5/18369 ,  H01S5/2222

Abstract: A surface-emitting-type semiconductor laser device having a buried structure wherein a burying part having a current blocking function is formed around a buried part comprising an active region. A reflecting mirror consisting of a semiconductor multilayer film is installed on the buried part and the burying part, and the Bragg wavelength of this semiconductor multilayer film is set in matching with a longitudinal mode one mode higher than the longitudinal mode of oscillation in pulse operation. This semiconductor multilayer film has a configuration wherein two kinds of GaAlAs layers having different composition ratios of Al are laminated alternately, and the layer thickness of each GaAlAS layer constituting the semiconductor multilayer film is set so as to able to realize the Bragg wavelength calculated theoretically.

Abstract translation: 具有掩埋结构的表面发射型半导体激光器件，其中具有电流阻挡功能的掩埋部分形成在包括有源区的掩埋部分周围。 由半导体多层膜组成的反射镜安装在掩埋部分和掩埋部分上，并且该半导体多层膜的布拉格波长被设定为与在脉冲操作中的纵向振荡模式相比更高的纵向模式匹配。 该半导体多层膜具有交替层叠具有不同组成比Al的两种GaAlAs层的构造，并且将构成半导体多层膜的各GaAlAS层的层厚度设定为能够实现理论上计算的布拉格波长。

公开(公告)号：US08803308B2

公开(公告)日：2014-08-12

申请号：US14137857

申请日：2013-12-20

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H01L23/495

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/15311

Abstract: A semiconductor device includes a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias, a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via; a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via, and a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal.

Abstract translation: 半导体器件包括在多个垂直堆叠的半导体芯片中的每一个上的多个信号端子，每个多个信号端子通过硅通孔连接到相邻半导体芯片的垂直排列的信号端子，多个信号端子中的每一个上的公共测试端子 通过硅通孔连接到相邻半导体芯片的垂直对准的公共测试端子的垂直堆叠的半导体芯片; 在多个垂直堆叠的半导体芯片上的多个螺旋测试端子，每个螺旋测试端子通过硅通孔连接到相邻半导体芯片的非垂直排列螺旋测试端子，以及沿着周边设置的导线 多个垂直堆叠的半导体芯片中的至少一个，连接到相应的公共测试端子的导线和相应的螺旋测试端子。