公开(公告)号：US08981501B2

公开(公告)日：2015-03-17

申请号：US13870706

申请日：2013-04-25

Applicant: United Microelectronics Corp.

Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

IPC: H01L29/84 ,  H01L21/311 ,  H01L23/48 ,  B81C1/00 ,  H01L27/06

CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

公开(公告)号：US20140319693A1

公开(公告)日：2014-10-30

申请号：US13870706

申请日：2013-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

IPC: H01L21/311 ,  H01L23/48

CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

公开(公告)号：US10737932B2

公开(公告)日：2020-08-11

申请号：US16284735

申请日：2019-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Sheng Lin ,  Jung-Hao Chang ,  Chang-Sheng Hsu ,  Weng-Yi Chen

IPC: B81B7/00 ,  B81C1/00

Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.

公开(公告)号：US10087072B2

公开(公告)日：2018-10-02

申请号：US15146741

申请日：2016-05-04

Applicant: United Microelectronics Corp.

Inventor： Chang-Sheng Hsu ,  Chih-Fan Hu ,  Chia-Wei Lee ,  En Chan Chen ,  Shih-Wei Li

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/66 ,  H01L29/66 ,  B81C1/00

Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.

公开(公告)号：US09961450B2

公开(公告)日：2018-05-01

申请号：US15246561

申请日：2016-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Sheng Hsu ,  Weng-Yi Chen ,  En-Chan Chen ,  Shih-Wei Li ,  Guo-Chih Wei

IPC: H01L29/84 ,  H04R17/02 ,  B81B3/00 ,  B81C1/00 ,  H04R31/00 ,  H04R19/00

CPC classification number: H04R17/025 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00158 ,  B81C2201/013 ,  H04R1/06 ,  H04R7/04 ,  H04R7/20 ,  H04R17/02 ,  H04R19/005 ,  H04R31/003 ,  H04R31/006 ,  H04R2201/003

Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.

公开(公告)号：US20170271529A1

公开(公告)日：2017-09-21

申请号：US15099610

申请日：2016-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzung-Han Tan ,  Chang-Sheng Hsu ,  Meng-Jia Lin ,  Te-Huang Chiu

IPC: H01L31/024 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/107

CPC classification number: H01L31/024 ,  H01L31/02327 ,  H01L31/035281 ,  H01L31/105 ,  H01L31/107 ,  H01L31/18 ,  H01L31/1804 ,  Y02E10/547

Abstract: An avalanche photodetector device includes a substrate having a front side and a back side, an avalanche photo detector structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality of reflecting islands disposed on the back side of the substrate.

公开(公告)号：US20160229692A1

公开(公告)日：2016-08-11

申请号：US14643183

申请日：2015-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Sheng Lin ,  Chang-Sheng Hsu ,  Meng-Jia Lin ,  Shih-Wei Li ,  Yan-Da Chen

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00238 ,  B81B2203/0127 ,  B81C2203/0792

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a base substrate and a MEMS structure. The base substrate comprises a CMOS structure. The MEMS structure is formed on the base substrate adjacent to the CMOS structure. The MEMS structure is connected to the CMOS structure. The MEMS structure comprises a membrane and a backplate. The base substrate has a cavity corresponding to the MEMS structure.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括基底和MEMS结构。 基底包括CMOS结构。 MEMS结构形成在与CMOS结构相邻的基底基板上。 MEMS结构连接到CMOS结构。 MEMS结构包括膜和背板。 基底衬底具有对应于MEMS结构的空腔。

公开(公告)号：US20160212551A1

公开(公告)日：2016-07-21

申请号：US14630620

申请日：2015-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Sheng Hsu ,  Yuan-Sheng Lin ,  Wei-Hua Fang ,  Kuan-Yu Wang ,  Yan-Da Chen

IPC: H04R23/00 ,  B81B3/00

CPC classification number: H04R23/00 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C1/00182 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003

Abstract: A microelectromechanical system microphone includes a semiconductor-on-insulator structure, a plurality of resistors, a plurality of first openings, and a vent hole. The semiconductor-on-insulator structure includes a substrate, an insulating layer and a semiconductor layer. The resistors are formed in the semiconductor layer, the first openings are formed in the semiconductor layer, and the vent hole is formed in the insulating layer and the substrate. The resistors are connected to each other to form a resistor pattern, and the first openings are all formed within the resistor pattern.

Abstract translation: 微机电系统麦克风包括绝缘体上半导体结构，多个电阻器，多个第一开口和通气孔。 绝缘体上半导体结构包括衬底，绝缘层和半导体层。 电阻器形成在半导体层中，第一开口形成在半导体层中，并且通气孔形成在绝缘层和基板中。 电阻器彼此连接以形成电阻器图案，并且第一开口都形成在电阻器图案内。