公开(公告)号：US09263276B2

公开(公告)日：2016-02-16

申请号：US12551292

申请日：2009-11-18

申请人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

公开(公告)号：US20090243031A1

公开(公告)日：2009-10-01

申请号：US12055682

申请日：2008-03-26

申请人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

发明人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

IPC分类号： H01L29/49 ,  H01L21/441

CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L29/517

摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

摘要翻译： 在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

公开(公告)号：US06905941B2

公开(公告)日：2005-06-14

申请号：US10250069

申请日：2003-06-02

申请人： Bruce B. Doris ,  Thomas S. Kanarsky ,  Meikei Ieong ,  Wesley C. Natzle

发明人： Bruce B. Doris ,  Thomas S. Kanarsky ,  Meikei Ieong ,  Wesley C. Natzle

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L21/76

CPC分类号： H01L21/84 ,  H01L21/76283

摘要： A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.

摘要翻译： 提供了一种用于防止在隔离的超薄Si沟道器件的有源器件区域下形成多晶硅的方法。 该方法使用化学氧化物去除（COR）处理步骤来防止托管架形成，而不是采用诸如HF的化学蚀刻剂的常规湿法蚀刻工艺。 还提供了绝缘体上硅（SOI）结构。 该结构包括至少位于掩埋绝缘层上的顶部含Si层; 以及位于顶部含Si层和掩埋绝缘层的一部分中的氧化物填充沟槽隔离区。 顶部含Si层下方没有底切区域。

公开(公告)号：US08492803B2

公开(公告)日：2013-07-23

申请号：US12274758

申请日：2008-11-20

申请人： Ricky S. Amos ,  Wesley C. Natzle ,  Siddhartha Panda ,  Brian L. Tessier

发明人： Ricky S. Amos ,  Wesley C. Natzle ,  Siddhartha Panda ,  Brian L. Tessier

IPC分类号： H01L29/80 ,  H01L21/335

CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.

摘要翻译： 通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。 在形成与栅电极相邻的间隔层之后，栅电极变薄。 此外，间隔层的高度也可以减小。 间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。 减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。 升高的源极/漏极层可以位于本征源极/漏极区域上。 凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。 此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。

公开(公告)号：US20090212332A1

公开(公告)日：2009-08-27

申请号：US12034941

申请日：2008-02-21

申请人： Xinlin Wang ,  Michael A. Gribelyuk ,  Wesley C. Natzle

发明人： Xinlin Wang ,  Michael A. Gribelyuk ,  Wesley C. Natzle

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/28114 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833

摘要： In a first structure, a metal gate portion may be laterally recessed from a substantially vertical surface of a gate conductor thereabove. A cavity is formed between the metal gate portion and a gate spacer. In a second structure, a disposable gate portion is removed after laterally recessing a metal gate portion therebeneath and forming a dielectric layer having a surface coplanar with a top surface of the disposable gate portion. (We have to include the inner spacer without a metal recess). An inner gate spacer is formed over a periphery of the metal gate portion provide a reduced overlap capacitance. In a third structure, a thin dielectric layer is employed to form a cavity next to the metal gate portion in conjunction with the inner gate spacer to provide reduced overlap capacitance.

摘要翻译： 在第一结构中，金属栅极部分可以从其上方的栅极导体的大致垂直的表面侧向凹入。 在金属栅极部分和栅极间隔物之间​​形成空腔。 在第二结构中，在横向凹入其上的金属栅极部分之后去除一次性栅极部分，并形成具有与一次性栅极部分的顶表面共面的表面的电介质层。 （我们必须包括没有金属凹槽的内衬垫）。 内栅间隔件形成在金属栅极部分的周边上，提供减小的重叠电容。 在第三结构中，采用薄的电介质层与内部栅极间隔物结合形成邻近金属栅极部分的空腔，以提供减小的重叠电容。

公开(公告)号：US06858903B2

公开(公告)日：2005-02-22

申请号：US10881449

申请日：2004-06-30

申请人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L27/76

CPC分类号： H01L21/31116 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/66628

摘要： A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

摘要翻译： 一种用于制造FET器件的工艺。 半导体衬底被栅极电介质层覆盖，并且在栅极电介质上形成导电栅电极。 可以加入氧化硅的毯层。 可以在栅电极周围的氧化硅层上形成可选的氮化硅环。 执行两个预清洗步骤。 然后沉积化学氧化物去除气体，用吸附的反应物膜覆盖该装置。 由于吸附的反应物膜与栅极电介质层反应，在栅电极的底部形成氧化硅的圆角，所以除去栅极电介质（除了栅电极之外）。 一个或两个原位掺杂的硅层沉积在源极/漏极区上，以在衬底上方突出超过栅极电介质的表面形成单个或层叠的外延凸起的源/漏区。

公开(公告)号：US5838045A

公开(公告)日：1998-11-17

申请号：US811982

申请日：1997-03-05

申请人： Karl Paul Ludwig Muller ,  Wesley C. Natzle

发明人： Karl Paul Ludwig Muller ,  Wesley C. Natzle

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10861 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L28/40

摘要： Isotropic deposition of a selectively etchable material in an opening in a body of material followed by isotropic deposition of an etch resistant material forms a mask for anisotropic etching of the selectively etchable material at potentially sub-lithographic dimensions to form potentially sub-lithographic features within a trench. This process can be exploited to form a folded trench capacitor in which a trench is formed with one or more upstanding and possibly hollow features therein; effectively multiplying the surface area and or allowing reduced trench depth for a given charge storage capacity or a combination thereof. Further surface treatments such as deposition of hemispherical grain silicon can be used to further enhance the effective area of the trench. Isolation structures of sub-lithographic dimensions can also be formed by depositing appropriate materials within the trenches formed in accordance with the mask.

摘要翻译： 可选择性蚀刻材料在材料体的开口中的各向同性沉积，随后是耐蚀刻材料的各向同性沉积形成掩模，用于在潜在的亚光刻尺寸下对可选择性蚀刻的材料进行各向异性蚀刻，以形成潜在的亚光刻特征 沟。 可以利用该过程形成折叠沟槽电容器，其中在其中形成有一个或多个直立和可能中空特征的沟槽; 对于给定的电荷存储容量或其组合，有效地乘以表面积和/或允许减小沟槽深度。 可以使用诸如半球形晶粒硅沉积的其它表面处理来进一步增强沟槽的有效面积。 亚光刻尺寸的隔离结构也可以通过在根据掩模形成的沟槽内沉积合适的材料来形成。

公开(公告)号：US5286331A

公开(公告)日：1994-02-15

申请号：US786448

申请日：1991-11-01

申请人： Lee Chen ,  Shwu-Jen Jeng ,  Wesley C. Natzle ,  Chienfan Yu

发明人： Lee Chen ,  Shwu-Jen Jeng ,  Wesley C. Natzle ,  Chienfan Yu

IPC分类号： C23F4/02 ,  C23F4/00 ,  H01L21/302 ,  H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31116 ,  C23F4/00

摘要： In supersonic molecular beam etching, the reactivity of the etchant gas and substrate surface is improved by creating etchant gas molecules with high internal energies through chemical reactions of precursor molecules, forming clusters of etchant gas molecules in a reaction chamber, expanding the etchant gas molecules and clusters of etchant gas molecules through a nozzle into a vacuum, and directing the molecules and clusters of molecules onto a substrate. Translational energy of the molecules and clusters of molecules can be improved by seeding with inert gas molecules. The process provides improved controllability, surface purity, etch selectivity and anisotropy. Etchant molecules may also be expanded directly (without reaction in a chamber) to produce clusters whose translational energy can be increased through expansion with a seeding gas.

摘要翻译： 在超音速分子束蚀刻中，蚀刻剂气体和衬底表面的反应性通过通过前体分子的化学反应产生具有高内能的蚀刻剂气体分子来改善，在反应室中形成蚀刻剂气体分子簇，使蚀刻剂气体分子膨胀， 蚀刻剂气体分子的簇通过喷嘴进入真空，并将分子和分子簇引导到基底上。 可以通过用惰性气体分子进行接种来改善分子和分子团簇的平移能。 该方法提供改进的可控性，表面纯度，蚀刻选择性和各向异性。 蚀刻剂分子也可以直接扩增（在室中没有反应）以产生其平移能量可以通过用接种气体膨胀而增加的簇。

公开(公告)号：US20120286374A1

公开(公告)日：2012-11-15

申请号：US13556795

申请日：2012-07-24

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/2822 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66575

摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

摘要翻译： 用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。 在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。 在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

公开(公告)号：US20110034000A1

公开(公告)日：2011-02-10

申请号：US12907186

申请日：2010-10-19

申请人： Ashima B. Chakravarti ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Wesley C. Natzle

发明人： Ashima B. Chakravarti ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Wesley C. Natzle

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13023 ,  H01L2924/1305 ,  H01L2924/00

摘要： A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

摘要翻译： 在半导体制造工艺中选择性地形成锗结构的方法在化学氧化物去除（COR）工艺中从氮化物表面去除天然氧化物，然后将加热的氮化物和氧化物表面暴露于加热的含锗气体，以仅选择性地形成锗 氮化物表面而不是氧化物表面。