公开(公告)号：US20150284244A1

公开(公告)日：2015-10-08

申请号：US14676738

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: B81C1/00 ,  H01L21/683 ,  H01L23/00 ,  H01L27/146 ,  H01L21/78

CPC classification number: B81C1/00896 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/11 ,  H01L24/43 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/0231 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/05432 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

Abstract translation: 提供了一种形成芯片封装的方法。 该方法包括提供衬底和覆盖层，其中衬底在其中邻近衬底的表面具有感测装置。 封盖层通过粘合剂层附接到基底的表面，其中粘合剂层覆盖感测装置。 沿着形成单个芯片封装的方向在衬底，粘合剂层和覆盖层上进行切割工艺。

公开(公告)号：US20140251946A1

公开(公告)日：2014-09-11

申请号：US14282457

申请日：2014-05-20

Applicant: XINTEC INC.

Inventor： Yi-Ming CHANG ,  I-Min LIN ,  Po-Shen LIN

IPC: H05K3/06

CPC classification number: H05K3/06 ,  H01L21/4853 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.

Abstract translation: 提供了一种用于改善冠状缺陷的布线结构及其制造方法。 该方法包括以下步骤。 提供了其上形成有种子层和具有开口的图案化光致抗蚀剂层的衬底。 在开口中形成有覆盖种子层的底部的铜层。 覆盖铜层的至少一个顶部的阻挡层形成在铜层上。 阻挡层的氧化电位大于铜层的氧化电位。 去除图案化的光致抗蚀剂层以进行蚀刻工艺，其中铜层和暴露的种子层的一部分被蚀刻以形成布线层。 进行浸渍处理以在阻挡层和布线层的暴露表面上综合地形成抗氧化层。

公开(公告)号：US20140015111A1

公开(公告)日：2014-01-16

申请号：US13941854

申请日：2013-07-15

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shih-Chin CHEN ,  Yi-Ming CHANG ,  Chien-Hui CHEN ,  Chia-Ming CHENG ,  Wei-Luen SUEN ,  Chen-Han CHIANG

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/1416 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 设置在所述基板中的装置区域; 位于半导体衬底的第一表面上的电介质层; 位于所述电介质层中并电连接到所述器件区域的多个导电焊盘; 设置在所述半导体衬底中并且从所述第二表面朝向所述第一表面延伸的至少一个对准标记。

公开(公告)号：US20170213805A1

公开(公告)日：2017-07-27

申请号：US15483928

申请日：2017-04-10

Applicant: XINTEC INC.

Inventor： Chia-Lun SHEN ,  Yi-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/32 ,  H01L21/30604 ,  H01L21/48 ,  H01L21/78 ,  H01L24/05 ,  H01L24/09 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

公开(公告)号：US20170148694A1

公开(公告)日：2017-05-25

申请号：US15358098

申请日：2016-11-21

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU

IPC: H01L23/053 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L21/561 ,  G06K9/0004 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/16225

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

公开(公告)号：US20160049436A1

公开(公告)日：2016-02-18

申请号：US14819348

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687

Abstract: A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A colour filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the colour filter. The carrier substrate is removed.

Abstract translation: 制造芯片封装的方法包括提供至少具有光电二极管和互连层的半导体衬底。 互连层设置在半导体衬底的上表面上并且在光电二极管之上并且电连接到光电二极管。 至少在互连层上形成再分布电路。 再分配电路电连接到互连层。 在再分配电路上形成封装层。 随后，将载体衬底附接到包装层。 滤色器形成在半导体衬底的下表面上。 在滤色器下方形成微透镜模块。 移除载体衬底。

公开(公告)号：US20150279808A1

公开(公告)日：2015-10-01

申请号：US14673657

申请日：2015-03-30

Applicant: XINTEC INC.

Inventor： Chia-Lun SHEN ,  Yi-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/78

CPC classification number: H01L24/32 ,  H01L21/30604 ,  H01L21/48 ,  H01L21/78 ,  H01L24/05 ,  H01L24/09 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

Abstract translation: 提供一种形成芯片封装的方法。 该方法包括提供第一基板和第二基板。 第一衬底通过粘合剂层附着到第二衬底上。 形成第一开口以穿透第一基底和粘合剂层，并将第一基底和粘合剂层分离成部分。 还提供了通过该方法形成的芯片封装。

公开(公告)号：US20140242742A1

公开(公告)日：2014-08-28

申请号：US14191348

申请日：2014-02-26

Applicant: XINTEC INC.

Inventor： Yi-Ming CHANG ,  Kuo-Hua LIU ,  Yi-Cheng WANG ,  Sheng-Yen CHANG

IPC: H01L31/0203 ,  H01L21/683

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/48091 ,  H01L2924/16235 ,  H01L2924/00014

Abstract: A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.

Abstract translation: 晶片封装方法包括以下步骤。 提供具有多个集成电路单元的晶片。 与集成电路单元相对的晶片的第一表面被研磨。 剥离层形成在透光载体的第二表面上。 在透光载体的第二表面或晶片的第三表面上形成紫外线临时粘接层。 紫外线暂时接合层用于将透光载体的第二表面粘附到晶片的第三表面。 晶片的第一表面粘附到紫外线带上。 透光载体的第四表面暴露于紫外线以消除紫外线临时粘合层的粘附力。 去除透光载体和释放层。