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    On chip detection of electrical overstress events
    11.
    发明授权
    On chip detection of electrical overstress events 有权
    片上检测电应力事件

    公开(公告)号：US09575111B1

    公开(公告)日：2017-02-21

    申请号：US13942626

    申请日：2013-07-15

    Applicant: Xilinx, Inc.

    Inventor： James Karp ,  Michael J. Hart ,  John K. Jennings

    IPC: H02H3/00 ,  G01R31/26 ,  H02H3/20 ,  H03K17/08

    CPC classification number: G01R31/26 ,  H02H3/00 ,  H02H3/20 ,  H03K17/08 ,  H03K19/00369

    Abstract: A system configured for detecting electrical overstress events within an integrated circuit includes a comparator configured to determine whether a monitored voltage level of a monitored signal exceeds an overstress reference voltage level. The overstress reference voltage level is a predetermined amount of voltage above a nominal voltage level for the monitored signal. The system further includes a write circuit coupled to an output of the comparator. The write circuit is configured to indicate an occurrence of an electrical overstress event within the integrated circuit responsive to the comparator determining that the monitored voltage level exceeds the overstress reference voltage level.

    Abstract translation: 配置用于检测集成电路内的过电压事件的系统包括：比较器，被配置为确定所监视的信号的监测电压电平是否超过过应力参考电压电平。 超应力参考电压电平是高于监视信号的额定电压电平的预定量的电压。 该系统还包括耦合到比较器的输出的写入电路。 写电路被配置为响应于比较器确定监视的电压电平超过过应力参考电压电平来指示集成电路内的电应力事件的发生。

    SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES
    15.
    发明申请
    SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES 审中-公开

    公开(公告)号：US20200066713A1

    公开(公告)日：2020-02-27

    申请号：US16110894

    申请日：2018-08-23

    Applicant: Xilinx, Inc.

    Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

    IPC: H01L27/06 ,  H01L27/02 ,  H01L29/73 ,  H01L29/78 ,  H01L49/02

    Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

    MITIGATION FOR FINFET TECHNOLOGY USING DEEP ISOLATION
    17.
    发明申请
    MITIGATION FOR FINFET TECHNOLOGY USING DEEP ISOLATION 审中-公开

    公开(公告)号：US20190280086A1

    公开(公告)日：2019-09-12

    申请号：US15917206

    申请日：2018-03-09

    Applicant: Xilinx, Inc.

    Inventor： James Karp ,  Michael J. Hart

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET transistor is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the in and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second oxide isolation layer has a thickness greater than a thickness of the first isolation layer.

    Circuit for and method of storing data in an integrated circuit device
    19.
    发明授权
    Circuit for and method of storing data in an integrated circuit device 有权

    公开(公告)号：US10263623B1

    公开(公告)日：2019-04-16

    申请号：US16107751

    申请日：2018-08-21

    Applicant: Xilinx, Inc.

    Inventor： Yanran Chen ,  Pierre Maillard ,  Michael J. Hart

    IPC: G11C17/18 ,  H03K19/173 ,  H03K17/00 ,  G11C11/412 ,  H03K19/003

    Abstract: A circuit for storing data in an integrated circuit is described. The circuit comprises an inverter comprising a first transistor having a first gate configured to receive input data and a first output configured to generate a first inverted data output and a second transistor having a second gate configured to receive the input data and a second output configured to generate a second inverted data output; a first pass gate coupled to the first output of the inverter; a second pass gate coupled to the second output of the inverter; and a storage element having an input coupled to receive an output of the first pass gate and an output of the second pass gate. A method of storing data in an integrated circuit is also described.

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