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公开(公告)号：US07915083B1
公开(公告)日：2011-03-29
申请号：US12588806
申请日：2009-10-28
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/03 , H01L21/76898 , H01L24/05 , H01L24/24 , H01L24/25 , H01L24/32 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/05541 , H01L2224/0555 , H01L2224/0556 , H01L2224/05599 , H01L2224/20 , H01L2224/94 , H01L2225/06551 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2224/83 , H01L2924/00 , H01L2224/05552
摘要： A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body has: a main part having a top surface and a bottom surface and including a plurality of layer portions stacked; and a plurality of terminals arranged on at least one of the top and bottom surfaces of the main part and electrically connected to the wiring. A manufacturing method for the layered chip package includes: fabricating a plurality of first layered substructures each including a plurality of pre-separation main bodies arrayed; fabricating a second layered substructure by stacking the first layered substructures; cutting the second layered substructure into a block in which a plurality of pre-separation main bodies are arrayed in two directions; forming the wiring simultaneously for the plurality of pre-separation main bodies included in the block; and separating the pre-separation main bodies from each other.
摘要翻译： 分层芯片封装包括主体和布置在主体的至少一个侧表面上的布线。 主体具有：具有顶面和底面的主要部分，并且包括堆叠的多个层部分; 以及多个端子，其布置在主要部件的顶表面和底表面中的至少一个上并电连接到布线。 层叠芯片封装的制造方法包括：制造多个第一分层子结构，每个第一分层子结构包括排列的多个预分离主体; 通过堆叠第一分层子结构制造第二分层子结构; 将第二分层子结构切割成多个预分离主体沿两个方向排列的块; 为包括在块中的多个预分离主体同时形成布线; 并将预分离主体彼此分离。
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公开(公告)号：US08362602B2
公开(公告)日：2013-01-29
申请号：US12852767
申请日：2010-08-09
IPC分类号： H01L23/02
CPC分类号： H01L25/50 , H01L23/5382 , H01L24/01 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2924/07802 , H01L2924/00
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.
摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括多个层部分; 多个第一端子，其设置在所述主体部的上表面并与所述布线连接; 以及多个第二端子，其设置在所述主体部的底面并与所述布线连接。 每个层部分包括半导体芯片。 多个第二端子被定位成在垂直于主体顶表面的方向上与多个第一端子重叠。 经由导线电连接的多对第一和第二端子包括定位为不彼此重叠的多对第一端子和第二端子。
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公开(公告)号：US20120013024A1
公开(公告)日：2012-01-19
申请号：US12835291
申请日：2010-07-13
IPC分类号： H01L23/522 , H01L21/50
CPC分类号： H01L23/522 , H01L21/563 , H01L21/6835 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05644 , H01L2224/05647 , H01L2224/1146 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/24146 , H01L2224/245 , H01L2224/2746 , H01L2224/29111 , H01L2224/29144 , H01L2224/2919 , H01L2224/32148 , H01L2224/81121 , H01L2224/8113 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/8313 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/9202 , H01L2224/92244 , H01L2224/94 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0105 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2224/81 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2221/68304
摘要： A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip, and a plurality of electrodes that are electrically connected to the wires. The electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip. In at least one of the layer portions, the first electrodes are in contact with and electrically connected to the semiconductor chip.
摘要翻译： 分层芯片封装包括主体和布线，所述布线包括设置在主体的侧表面上的多根布线。 主体包括主要部分和多个端子。 主要部分包括堆叠的多个层部分。 端子设置在主要部件的顶表面和底表面中的至少一个中并电连接到电线。 每个层部分包括半导体芯片和电连接到导线的多个电极。 电极包括旨在建立与半导体芯片的电连接的多个第一电极和不与半导体芯片接触的多个第二电极。 在至少一个层部分中，第一电极与半导体芯片接触并电连接。
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公开(公告)号：US20110316141A1
公开(公告)日：2011-12-29
申请号：US12822601
申请日：2010-06-24
IPC分类号： H01L23/485 , H01L21/60 , H01L21/822
CPC分类号： H01L21/6835 , H01L21/563 , H01L21/76898 , H01L23/522 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02317 , H01L2224/02321 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05554 , H01L2224/05644 , H01L2224/05647 , H01L2224/1146 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/24146 , H01L2224/245 , H01L2224/2746 , H01L2224/29144 , H01L2224/2919 , H01L2224/32148 , H01L2224/81121 , H01L2224/8113 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/83121 , H01L2224/8313 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/85 , H01L2224/9202 , H01L2224/92244 , H01L2224/94 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2224/81 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2221/68304
摘要： A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.
摘要翻译： 分层芯片封装包括主体和布置在主体的侧表面上的布线。 主体包括：主要部分，其包括堆叠的多个层部分; 多个第一端子，其设置在所述主体部的上表面并与所述布线连接; 以及多个第二端子，其设置在所述主体部的底面并与所述布线连接。 多个层部分包括第一类型层部分和第二类型部分。 第一型层部分包括符合半导体芯片和连接到半导体芯片和布线的多个第一类型电极。 第二型层部分包括有缺陷的半导体芯片，以及多个第二类型电极，其连接到布线而不连接到半导体芯片。
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公开(公告)号：US08466562B2
公开(公告)日：2013-06-18
申请号：US12585778
申请日：2009-09-24
IPC分类号： H01L23/48
CPC分类号： H01L24/94 , H01L23/481 , H01L24/11 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05554 , H01L2224/0557 , H01L2224/1147 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/3025 , H01L2224/05552
摘要： A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.
摘要翻译： 分层芯片封装包括堆叠的多个层部分，每个层部分包括半导体芯片。 多个层部分包括至少一个第一类型层部分和至少一个第二类型的部分。 半导体芯片具有电路，电连接到电路的多个电极焊盘以及多个贯通电极。 在每个垂直相邻的两个层部分中，两个层部分中的一个的半导体芯片的多个通孔电连接到两个层部分中另一个的半导体芯片的相应的贯通电极。 第一型层部分包括用于将多个贯通电极电连接到各个对应的电极焊盘的多条导线，而第二型层部分不包括导线。
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公开(公告)号：US08441112B2
公开(公告)日：2013-05-14
申请号：US12896283
申请日：2010-10-01
CPC分类号： H01L25/50 , H01L22/22 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/08145 , H01L2224/13025 , H01L2224/131 , H01L2224/32145 , H01L2224/73267 , H01L2224/97 , H01L2225/06524 , H01L2225/06527 , H01L2225/06558 , H01L2225/1035 , H01L2225/1064 , H01L2924/01029 , H01L2924/07802 , H01L2924/3511 , H01L2224/19 , H01L2224/83 , H01L2924/00 , H01L2924/014
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.
摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括第一和第二层部分; 以及多个第一和第二端子，其分别设置在主要部分的顶表面和底表面上，并且电连接到多个导线。 第一和第二端子通过使用第一和第二层部分的电极形成。 层叠芯片封装通过层叠两个子结构（其中包括多个预备层部分的阵列），然后切割层状子结构而制造层状子结构来制造。 分层子结构包括多个初级线，其布置在两个相邻的预分离主体之间并且将成为多根线。
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公开(公告)号：US08358015B2
公开(公告)日：2013-01-22
申请号：US13156941
申请日：2011-06-09
CPC分类号： H01L23/5389 , H01L21/561 , H01L21/6835 , H01L22/22 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/0235 , H01L2224/02371 , H01L2224/02373 , H01L2224/02379 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05013 , H01L2224/05147 , H01L2224/05644 , H01L2224/1146 , H01L2224/13024 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/2405 , H01L2224/24146 , H01L2224/245 , H01L2224/2512 , H01L2224/25171 , H01L2224/25175 , H01L2224/25177 , H01L2224/2746 , H01L2224/29024 , H01L2224/29144 , H01L2224/32145 , H01L2224/32148 , H01L2224/75101 , H01L2224/8112 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/8313 , H01L2224/83191 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/83986 , H01L2224/92 , H01L2224/92244 , H01L2224/94 , H01L2224/95 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06565 , H01L2225/1058 , H01L2924/07802 , H01L2924/0105 , H01L2224/82 , H01L2924/00014 , H01L2224/83 , H01L2224/11 , H01L2224/27 , H01L2224/0231 , H01L21/78 , H01L2224/81 , H01L2924/00
摘要： A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.
摘要翻译： 分层芯片封装包括主体和布线。 主体包括：具有顶表面和底表面并且包括彼此堆叠的三个或更多个层部分的主要部分; 多个第一端子，设置在所述主要部件的顶表面上; 以及设置在主要部分的底表面上的多个第二端子。 每个层部分包括具有第一和第二表面的半导体芯片和电连接到布线的多个电极。 多个电极设置在半导体芯片的第一表面的一侧。 位于最靠近主要部分的顶表面的第一层部分和最靠近主要部分的底表面的第二层部分被布置成使得它们各自的半导体芯片的第二表面朝向彼此。 多个第一端子通过使用第一层部分的多个电极形成。 多个第二端子通过使用第二层部分的多个电极形成。
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公开(公告)号：US08203215B2
公开(公告)日：2012-06-19
申请号：US12835291
申请日：2010-07-13
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/563 , H01L21/6835 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05644 , H01L2224/05647 , H01L2224/1146 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/24146 , H01L2224/245 , H01L2224/2746 , H01L2224/29111 , H01L2224/29144 , H01L2224/2919 , H01L2224/32148 , H01L2224/81121 , H01L2224/8113 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/8313 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/9202 , H01L2224/92244 , H01L2224/94 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0105 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2224/81 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2221/68304
摘要： A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip, and a plurality of electrodes that are electrically connected to the wires. The electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip. In at least one of the layer portions, the first electrodes are in contact with and electrically connected to the semiconductor chip.
摘要翻译： 分层芯片封装包括主体和布线，所述布线包括设置在主体的侧表面上的多根布线。 主体包括主要部分和多个端子。 主要部分包括堆叠的多个层部分。 端子设置在主要部件的顶表面和底表面中的至少一个中并电连接到电线。 每个层部分包括半导体芯片和电连接到导线的多个电极。 电极包括旨在建立与半导体芯片的电连接的多个第一电极和不与半导体芯片接触的多个第二电极。 在至少一个层部分中，第一电极与半导体芯片接触并电连接。
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公开(公告)号：US20120032318A1
公开(公告)日：2012-02-09
申请号：US12852767
申请日：2010-08-09
CPC分类号： H01L25/50 , H01L23/5382 , H01L24/01 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2924/07802 , H01L2924/00
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.
摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括多个层部分; 多个第一端子，其设置在所述主体部的上表面并与所述布线连接; 以及多个第二端子，其设置在所述主体部的底面并与所述布线连接。 每个层部分包括半导体芯片。 多个第二端子被定位成在垂直于主体顶表面的方向上与多个第一端子重叠。 经由导线电连接的多对第一和第二端子包括定位为不彼此重叠的多对第一端子和第二端子。
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公开(公告)号：US20110068456A1
公开(公告)日：2011-03-24
申请号：US12585778
申请日：2009-09-24
IPC分类号： H01L25/065 , H01L21/50 , H01L21/66
CPC分类号： H01L24/94 , H01L23/481 , H01L24/11 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05554 , H01L2224/0557 , H01L2224/1147 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/3025 , H01L2224/05552
摘要： A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.
摘要翻译： 分层芯片封装包括堆叠的多个层部分，每个层部分包括半导体芯片。 多个层部分包括至少一个第一类型层部分和至少一个第二类型的部分。 半导体芯片具有电路，电连接到电路的多个电极焊盘以及多个贯通电极。 在每个垂直相邻的两个层部分中，两个层部分中的一个的半导体芯片的多个通孔电连接到两个层部分中另一个的半导体芯片的相应的贯通电极。 第一型层部分包括用于将多个贯通电极电连接到各个对应的电极焊盘的多条导线，而第二型层部分不包括导线。
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