公开(公告)号：US11817378B2

公开(公告)日：2023-11-14

申请号：US17364220

申请日：2021-06-30

Applicant: QUALCOMM INCORPORATED

Inventor： Nelly Chen ,  Gary Yao Zhang ,  Michael Randy May ,  Shrinivas Gopalan Uppili ,  Varin Sriboonlue

IPC: H05K1/02 ,  H01L23/498 ,  H01L23/66 ,  H05K3/34

CPC classification number: H01L23/49816 ,  H01L23/66 ,  H05K1/0228 ,  H05K3/3436 ,  H01L2223/6605 ,  H05K2201/09227 ,  H05K2201/10098 ,  H05K2201/10734

Abstract: A pin map covers a surface area of a layer of a printed circuit board (PCB). The pin map includes a plurality of electrical designations for each pin in the pin map and a plurality of empty spaces within the pin map. Each electrical designation may be assigned to a pin on the pin map. Each electrical designation includes a positive polarity (P+) pin, a negative polarity (P−) pin, or an electrical ground (G) pin. If a space in the pin map does not have an electrical designation, then it may include an empty space/plain portion of the printed circuit board (PCB). The pin map may include a plurality of rows and a first repeating pin polarity pattern. The first repeating pin polarity pattern may include a lane unit tile. The pin map may help couple two circuit elements together that are attached to one layer of a PCB.

公开(公告)号：US11792933B2

公开(公告)日：2023-10-17

申请号：US17389306

申请日：2021-07-29

Applicant: Fermi Research Alliance, LLC

Inventor： Juan Estrada ,  Guillermo Fernandez Moroni ,  Andrew G. Lathrop ,  Javier Tiffenberg

IPC: H05K1/18 ,  H01R43/26 ,  H05K1/02 ,  H01R43/20 ,  H05K3/28 ,  H05K3/02 ,  H01R13/621

CPC classification number: H05K1/18 ,  H01R43/205 ,  H01R43/26 ,  H05K1/0216 ,  H05K3/282 ,  H01R13/6215 ,  H05K3/02 ,  H05K2201/0715 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/10189 ,  H05K2201/10507

Abstract: Systems, methods, and apparatus that employ a connector assembly having a substrate layer with an inner aperture and an outer periphery, and one or more signal traces disposed on the substrate that extend from an inner first location to an outer second location of the apparatus, for communicating data between electronic devices positioned within an interior volume of an enclosed vessel and complementary electronic devices positioned in an ambient environment external to the enclosed vessel. An inner connector is conductively connected the signal traces at the inner first location of each signal trace, and an outer connector is conductively connected to the one or more signal traces at the outer second location of each signal trace. A substantially flat exterior surface extends radially over at least a portion of a region between the respective first locations and the respective second locations.

公开(公告)号：US20230300976A1

公开(公告)日：2023-09-21

申请号：US18324402

申请日：2023-05-26

Applicant: Yungu (Gu’an) Technology Co., Ltd.

Inventor： Hongrui LI ,  Rusheng LIU ,  Hongqing FENG ,  Cuili GAI ,  Bing ZHANG

IPC: H05K1/02

CPC classification number: H05K1/0296 ,  H05K2201/09227

Abstract: A display panel includes: a substrate; a plurality of pixel units arranged on the substrate in an array along a first direction and a second direction intersecting each other, each of the pixel units includes N sub-pixels; and a plurality of pixel circuit units arranged on the substrate, each of the pixel circuit units includes N pixel circuits, each of the pixel circuits is electrically connected to a corresponding one of the sub-pixels, each of the pixel circuit units is provided with at least one arrangement unit, and in the arrangement unit, M pixel circuits are arranged adjacently in sequence, an arrangement direction of the pixel circuits in the arrangement unit includes a first tilted direction which is tilted with respect to both of the first direction and the second direction.

公开(公告)号：US11744023B2

公开(公告)日：2023-08-29

申请号：US17149858

申请日：2021-01-15

Applicant: Gentherm Inc.

Inventor： Timothy Hughes

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/12 ,  H05K3/46 ,  B60R16/02

CPC classification number: H05K3/4626 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/04 ,  H05K3/1225 ,  B60R16/0207 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/09227 ,  H05K2203/0228 ,  H05K2203/107 ,  H05K2203/166

Abstract: A method for manufacturing a dual conductor laminated substrate includes providing a first laminate including a first insulating layer and a first conductive layer; defining a first trace pattern including one or more traces in the first laminate; providing a second laminate including a second insulating layer and a second conductive layer; defining a second trace pattern including one or more traces in the second laminate; defining access holes in the second insulating layer; at least one of depositing and stenciling a conductive material in the access holes of the second insulating layer; and aligning and attaching the first laminate to the second laminate to create a laminated substrate.

公开(公告)号：US11723149B2

公开(公告)日：2023-08-08

申请号：US17158164

申请日：2021-01-26

Applicant: Kioxia Corporation

Inventor： Stephen Pardoe

IPC: H05K1/16 ,  H05K1/11 ,  H05K3/04 ,  H05K3/40

CPC classification number: H05K1/162 ,  H05K1/115 ,  H05K3/04 ,  H05K3/4038 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2203/0228

Abstract: A method of running a printed circuit board (PCB) trace on a PCB. The PCB comprising a plurality of PCB layers. The method comprising forming a conductive trace on at least one of the plurality of PCB layers; coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers; coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance. The capacitor is separated laterally in a plan view at a first distance from the first via. The length of the conductive trace in the plan view is greater than the first distance. The conductive path of the conductive trace of the length has the predetermined impedance.

公开(公告)号：US20230199952A1

公开(公告)日：2023-06-22

申请号：US18066473

申请日：2022-12-15

Applicant: Exro Technologies Inc.

Inventor： Eric HUSTEDT

IPC: H05K1/11 ,  H05K1/18 ,  H02M7/00

CPC classification number: H05K1/111 ,  H05K1/181 ,  H02M7/003 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/10166 ,  H05K2201/10522

Abstract: An article for a power inverter, includes a multilayer printed circuit board having a first and second electrically conductive wiring layer and at least a first dielectric layer interposed between the first and second electrically conductive wiring layers. Each conductive wiring layer includes a common input and output line, the common input and output lines at least partially overlapping one another in a projection along a thickness of the multilayer printed circuit board. A set of input mounting pads is carried by the first common input line and a set of input mounting pads is carried by the second common input line, the input mounting pads of the second set of input mounting pads are interleaved with the input mounting pads of the first set of input mounting pads along a first axis. The article further includes a set output mounting pads carried by the common output line.

公开(公告)号：US11678437B2

公开(公告)日：2023-06-13

申请号：US17210907

申请日：2021-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyun Seok ,  Gyu Chae Lee ,  Jeong Hyeon Cho

IPC: H05K1/18 ,  H01L25/18 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L25/18 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal be is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.

公开(公告)号：US11662612B2

公开(公告)日：2023-05-30

申请号：US16690522

申请日：2019-11-21

Applicant: EAGLE TECHNOLOGY, LLC

Inventor： Peter A. Wasilousky ,  Christopher A. Corey ,  Carrigan L. Braun ,  Michael R. Lange ,  Catheryn D. Logan ,  Randall K. Morse

IPC: G02F1/11 ,  G06N10/00 ,  G02F1/01 ,  G02F1/33 ,  H01S5/00 ,  H05K1/11 ,  H05K3/40

CPC classification number: G02F1/113 ,  G02F1/0102 ,  G02F1/11 ,  G02F1/33 ,  G02F1/332 ,  G06N10/00 ,  H01S5/005 ,  H01S5/0085 ,  H05K1/11 ,  H05K1/115 ,  H05K3/4038 ,  H05K2201/09227 ,  H05K2201/10121

Abstract: An acousto-optic system may include a laser source, and an AOM coupled to the laser source and having an acousto-optic medium and transducer electrodes carried by the medium. The acousto-optic system may also include an interface board with a dielectric layer and signal contacts carried by the dielectric layer, and connections coupling respective signal contacts with respective transducer electrodes. Each connection may include a dielectric protrusion extending from the AOM, and an electrically conductive layer on the dielectric protrusion for coupling a respective transducer electrode to a respective signal contact.

公开(公告)号：US11646056B2

公开(公告)日：2023-05-09

申请号：US17527027

申请日：2021-11-15

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Yuki Sato

IPC: G11B5/48 ,  H05K1/11 ,  H01R12/61 ,  H01R4/04

CPC classification number: G11B5/4853 ,  G11B5/486 ,  H01R12/61 ,  H05K1/116 ,  H05K1/118 ,  H01R4/04 ,  H01R2201/06 ,  H05K2201/09227 ,  H05K2201/09409

Abstract: A disk device according to one embodiment includes a recording medium, a magnetic head, a wiring member, and a flexible printed circuit board. The magnetic head is configured to read/write information from/to the recording medium. The wiring member includes a plurality of first terminals, and a plurality of first wires that electrically connect the magnetic head to the first terminals. The flexible printed circuit board includes a surface, a plurality of second terminals located on the surface to be connected to the first terminals by means of a conductive adhesive, and a ground plane spaced apart from the second terminals in a direction along the surface.

公开(公告)号：US20190208618A1

公开(公告)日：2019-07-04

申请号：US16234829

申请日：2018-12-28

Applicant: CELESTICA TECHNOLOGY CONSULTANCY (SHANGHAI) CO. LTD

Inventor： JIWEI WEN ,  CHENXIA FENG ,  LIANG CHEN ,  LIJUAN QU

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04

CPC classification number: H05K1/0216 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/043 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09672 ,  H05K2203/0207

Abstract: The present invention provides a high speed signal fan-out method for BGA and a PCB using the same. The method comprises: providing a printed circuit board (PCB), providing a plurality of vias and signal traces of the vias on the PCB; and providing back-drilled holes for routing of other signal traces at positions corresponding to the vias. The vias are arranged into a plurality of straight lines from an edge to the center of the PCB. The plurality of straight lines each is horizontal or vertical. The signal traces of the vias in a straight line are arranged from high to low or from low to high with respect to routing positions of the vias, and the back-drilled holes of the plurality of vias are arranged in descending or ascending order corresponding to the depths of the back-drilled holes.