公开(公告)号：US5616962A

公开(公告)日：1997-04-01

申请号：US348128

申请日：1994-11-28

Applicant: Toshimitsu Ishikawa ,  Atsushi Kitamura ,  Kenji Hirayama

Inventor： Toshimitsu Ishikawa ,  Atsushi Kitamura ,  Kenji Hirayama

IPC: H05K13/04 ,  H01L23/31 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H01L23/28 ,  H01L23/50

CPC classification number: H01L23/3107 ,  H01L25/105 ,  H05K1/181 ,  H05K3/303 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/1053 ,  H05K2201/10537 ,  H05K2201/10696 ,  H05K3/3421 ,  Y02P70/611 ,  Y02P70/613

Abstract: A method of mounting semiconductor integrated circuit devices comprising steps of forming a semiconductor device block having a plurality of semiconductor integrated circuit devices of vertical mounting type coupled to each other in parallel, and mounting the semiconductor device block on a printed board. A block of semiconductor integrated circuit devices comprising a plurality of semiconductor integrated circuit devices of vertical mounting type, and coupling means for coupling the plurality of semiconductor integrated circuit devices each other in parallel.

Abstract translation: 一种安装半导体集成电路器件的方法，包括以下步骤：形成具有并联耦合的多个垂直安装型的多个半导体集成电路器件的半导体器件块，以及将半导体器件块安装在印刷电路板上。 一种半导体集成电路器件，包括垂直安装型的多个半导体集成电路器件，以及用于将多个半导体集成电路器件并联连接的耦合器件。

公开(公告)号：US5450289A

公开(公告)日：1995-09-12

申请号：US206179

申请日：1994-03-07

Applicant: Yooung D. Kweon ,  Min C. An

Inventor： Yooung D. Kweon ,  Min C. An

IPC: H01L23/495 ,  H05K1/18 ,  H05K3/34 ,  H01R9/00 ,  H05K7/02

CPC classification number: H01L23/49555 ,  H05K1/183 ,  H05K3/3426 ,  H01L2924/0002 ,  H05K2201/09036 ,  H05K2201/09709 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y02P70/613

Abstract: An arrangement for vertically mounting a semiconductor device to a substrate, e.g., a printed circuit board (PCB), in which a plurality of sequentially arranged external leads of the semiconductor device include at least three different sets of non-consecutive ones of the external leads which have laterally outwardly extending foot portions lying in respective, vertically spaced-apart planes, and in which the foot portions of first and second ones of the sets of non-consecutive external leads are respectively secured to respective first and second steps formed in one of a plurality of walls defining a cavity in the PCB, and a third set of the non-consecutive external leads are secured to a portion of a major surface of the PCB adjacent the cavity.

Abstract translation: 用于将半导体器件垂直安装到衬底（例如印刷电路板（PCB））的布置，其中半导体器件的多个顺序排列的外部引线包括至少三个不同的一组不连续的外部引线 其具有位于相应的，垂直间隔开的平面中的横向向外延伸的脚部分，并且其中第一和第二组非连续外部引线的脚部分别固定到相应的第一和第二台阶， 在PCB中限定空腔的多个壁，以及第三组非连续外部引线固定到邻近空腔的PCB的主表面的一部分。

公开(公告)号：US5204287A

公开(公告)日：1993-04-20

申请号：US723108

申请日：1991-06-28

Applicant: Robert N. McLellan ,  Anthony M. Chiu

Inventor： Robert N. McLellan ,  Anthony M. Chiu

IPC: H01L21/60 ,  H01L23/28 ,  H01L23/495 ,  H05K3/30

CPC classification number: H05K3/301 ,  H01L23/49555 ,  H05K3/303 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49121 ,  Y10T29/49139

Abstract: An electronic device (10) includes a package (16) having two posts (30) suitable for insertion in PCB holes. Package (16) presents a lengthwise molding plane (32) along which the upper portion (42) and bottom portion (44) of package (16) are mated during the molding process. Posts (30) are disposed substantially exclusively in bottom portion (44) so that posts (30) are asymmetric about lengthwise molding plane (32). Thus, even if a top mold (42a) and a bottom mold (44a) are misaligned there will be no effect on the dimensional tolerance of posts (30) and thus the tolerance of post (30) can be closely matched with a PCB hole (20) tolerance to insure a snug fit. Thus, device (10) is mounted edgewise on a PCB (18) by insertion of posts (30) into PCB holes (20) so that tips (24) of lead fingers (14) can be connected to PCB (18) by surfacing-mounting techniques or the like.

公开(公告)号：US20060201705A1

公开(公告)日：2006-09-14

申请号：US11433721

申请日：2006-05-12

Applicant: Akram Salman ,  Warren Farnworth ,  Alan Wood ,  J. Brooks ,  Eugene Cloud

Inventor： Akram Salman ,  Warren Farnworth ,  Alan Wood ,  J. Brooks ,  Eugene Cloud

IPC: H05K1/18

CPC classification number: H05K3/4007 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/095 ,  H05K3/321 ,  H05K3/325 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10696 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

公开(公告)号：US20030007340A1

公开(公告)日：2003-01-09

申请号：US10237645

申请日：2002-09-09

Inventor： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  J. Michael Brooks ,  Eugene H. Cloud

IPC: H05K007/02 ,  H05K007/04

CPC classification number: H05K3/4007 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/095 ,  H05K3/321 ,  H05K3/325 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10696 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

公开(公告)号：US06342731B1

公开(公告)日：2002-01-29

申请号：US09002160

申请日：1997-12-31

Applicant: Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

Inventor： Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

IPC: H01L2302

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device including a plurality of stub contacts extending perpendiculary from a bottom edge thereof. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.

Abstract translation: 一种垂直安装的半导体器件，包括从其底部边缘延伸的多个短截线触点。 互补对准装置包括用于接收垂直安装的半导体器件的插座。 对准装置可附接到载体基板。 在将对准装置附接到载体基板并将可垂直安装的半导体装置插入到插座中时，接触元件向垂直安装的半导体器件施加向下的力，以建立并保持可垂直安装的半导体器件与 载体衬底。

公开(公告)号：US20010026023A1

公开(公告)日：2001-10-04

申请号：US09873869

申请日：2001-06-04

Inventor： Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

IPC: H01L023/544

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.

Abstract translation: 一种可垂直安装的半导体器件，包括从其底部边缘垂直延伸的多个短截线触点。 互补对准装置包括用于接收垂直安装的半导体器件的插座。 对准装置可附接到载体基板。 在将对准装置附接到载体基板并将可垂直安装的半导体装置插入到插座中时，接触元件向垂直安装的半导体器件施加向下的力，以建立并保持可垂直安装的半导体器件与 载体衬底。

公开(公告)号：US6134111A

公开(公告)日：2000-10-17

申请号：US060562

申请日：1998-04-15

Applicant: Larry D. Kinsman ,  Jerry M. Brooks ,  Walter L. Moden

Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Walter L. Moden

IPC: H01L23/367 ,  H01L23/433 ,  H05K1/02 ,  H05K3/30 ,  H05K7/02

CPC classification number: H05K3/303 ,  H01L23/3675 ,  H01L23/4334 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K2201/09709 ,  H05K2201/10454 ,  H05K2201/10659 ,  H05K2201/10696 ,  Y02P70/613

Abstract: A high density vertical surface mount package and thermal carrier therefor including a heat sink.

公开(公告)号：US5831332A

公开(公告)日：1998-11-03

申请号：US739218

申请日：1996-10-29

Applicant: Michio Sono ,  Junichi Kasai ,  Masanori Yoshimoto ,  Kazuto Tsuji ,  Kouji Saito

Inventor： Michio Sono ,  Junichi Kasai ,  Masanori Yoshimoto ,  Kazuto Tsuji ,  Kouji Saito

IPC: H01L23/482 ,  H01L23/495 ,  H01L23/58 ,  H05K3/30 ,  H05K3/34

CPC classification number: H05K3/303 ,  H01L23/49555 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01079 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K3/3426 ,  Y02P70/613

Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.

公开(公告)号：US5349235A

公开(公告)日：1994-09-20

申请号：US111518

申请日：1993-08-25

Applicant: Joon K. Lee ,  Hyeon J. Jeong ,  Kyung S. Kim ,  Oh-Sik Kwon

Inventor： Joon K. Lee ,  Hyeon J. Jeong ,  Kyung S. Kim ,  Oh-Sik Kwon

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/04 ,  H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H05K1/18 ,  H05K3/30 ,  H01L23/16

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/49555 ,  H05K3/303 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10696 ,  Y02P70/613

Abstract: A semiconductor chip package comprises leads which protrude from one side of a package body, and support portions which are formed at both ends of the package body on either side of the leads for firmly mounting the package on a printed circuit board (PCB). The support portions are made of a same material as the package body. At the package body, a slot is formed to further protect the leads, and the leads are alternately formed to mount the packages close by. Thus, there is no additional process step for forming holes in the PCB to mount the support portions of the semiconductor package, so the mounting process of the package becomes simpler. The support portions which protrude from the package body permit the package to be mounted on the PCB firmly. The slot and support portions protect the leads and prevent the leads from being deformed by external forces, thereby improving the reliability of the semiconductor package. Also, since the leads are alternately formed and the packages can be mounted near to each other, the package occupies only a small area of the PCB, thereby improving the packing density.

Abstract translation: 半导体芯片封装包括从封装主体的一侧突出的引线，以及在引线的两侧形成在封装主体的两端的支撑部分，用于将封装牢固地安装在印刷电路板（PCB）上。 支撑部分由与包装体相同的材料制成。 在封装主体上，形成一个槽以进一步保护引线，并且引线交替地形成为将封装安装在靠近处。 因此，没有用于在PCB中形成孔以安装半导体封装的支撑部分的附加工艺步骤，因此封装的安装过程变得更简单。 从包装体突出的支撑部分使得包装件能够牢固地安装在PCB上。 槽和支撑部分保护引线并防止引线由于外力而变形，从而提高半导体封装的可靠性。 此外，由于引线交替形成并且封装可以彼此靠近地安装，所以封装仅占用PCB的小面积，从而提高封装密度。