公开(公告)号：US09721946B2

公开(公告)日：2017-08-01

申请号：US15298124

申请日：2016-10-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Je-Hsiung Jeffrey Lan ,  Changhan Hobie Yun ,  Jonghae Kim

IPC: H01L29/93 ,  H01L27/108 ,  H01L21/70 ,  H01L21/8238 ,  H01L27/08 ,  H01L29/66 ,  H01L21/762 ,  H01L27/12 ,  H01L21/78

CPC classification number: H01L27/0808 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/78 ,  H01L27/1203 ,  H01L29/66174 ,  H01L29/66181 ,  H01L29/93

Abstract: A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

公开(公告)号：US09666362B2

公开(公告)日：2017-05-30

申请号：US15046302

申请日：2016-02-17

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H01F5/00 ,  H01F41/04 ,  H01F27/28 ,  H01F27/29 ,  H01F17/00 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

公开(公告)号：US20170134007A1

公开(公告)日：2017-05-11

申请号：US15410223

申请日：2017-01-19

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Chi Shun Lo ,  Jonghae Kim ,  Mario Francisco Velez ,  John H. Hong

IPC: H03H11/28 ,  H01F41/02 ,  H01L23/66 ,  H01L49/02 ,  H01L27/12 ,  H01L23/522

CPC classification number: H03H11/28 ,  H01F41/02 ,  H01F2019/085 ,  H01F2027/2809 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/13 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/30111 ,  H01L2924/00

Abstract: A method includes forming a replica circuit above a surface of a glass-type material. The replica circuit includes a thin-film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The method further includes forming a transformer above the surface of the glass-type material. The transformer is coupled to the replica circuit, and the transformer is configured to facilitate an impedance match between the replica circuit and an antenna.

公开(公告)号：US20170117358A1

公开(公告)日：2017-04-27

申请号：US14920851

申请日：2015-10-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L29/06 ,  H01L21/78 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/823481 ,  H01L23/3128 ,  H01L23/481 ,  H01L29/78

Abstract: Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

公开(公告)号：US09620463B2

公开(公告)日：2017-04-11

申请号：US14634148

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L23/552 ,  H01L23/60 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/60 ,  H01L21/568 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/00 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.

公开(公告)号：US20170033429A1

公开(公告)日：2017-02-02

申请号：US15149841

申请日：2016-05-09

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Chengjie Zuo ,  Je-Hsiung Jeffrey Lan ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01P7/06 ,  H01P7/10

CPC classification number: H01P7/06 ,  H01P7/10

Abstract: An apparatus includes a tunable cavity resonator that includes conductive walls that form a tunable cavity. The tunable cavity has first dimensions when one or more phase change material layers within the tunable cavity have a first state. The tunable cavity has second dimensions when the one or more phase change material layers have a second state.

Abstract translation: 一种装置包括可调谐腔谐振器，其包括形成可调谐空腔的导电壁。 当可调谐空腔内的一个或多个相变材料层具有第一状态时，可调谐空腔具有第一尺寸。 当一个或多个相变材料层具有第二状态时，可调谐腔具有第二维度。

公开(公告)号：US09560745B2

公开(公告)日：2017-01-31

申请号：US14498230

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Je-Hsiung Jeffrey Lan ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  David Francis Berdy

IPC: H01L21/768 ,  H05K1/02 ,  C23F1/02 ,  H05K1/03 ,  H05K1/09 ,  H01L23/00

CPC classification number: H05K1/0271 ,  C23F1/02 ,  H01L21/768 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0154 ,  H05K2201/0195 ,  H01L2924/00

Abstract: A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed.

Abstract translation: 器件包括在衬底（例如，半导体管芯或其他集成电路）的至少两个应力结构域之间的应力消除区域。 应力消除区域包括导电结构，电耦合应力区域的电路，导电结构设置在该应力区域之间。

公开(公告)号：US09548350B2

公开(公告)日：2017-01-17

申请号：US14177072

申请日：2014-02-10

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Daeik Daniel Kim ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Donald William Kidwell, Jr. ,  Jon Bradley Lasiter ,  Kwan-Yu Lai ,  Jitae Kim ,  Ravindra Vaman Shenoy

IPC: H01L29/00 ,  H01L49/02 ,  H01L27/08 ,  H01L23/48 ,  H01G4/33 ,  H01G4/012 ,  H01L21/48 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract translation: 提供的空间效率电容器具有比传统设计更高的品质因数，并且改善了从直通玻璃通孔（TGV）到电介质的电能的耦合。 例如，提供了具有非矩形横截面的TGV，其中TGV的一端耦合到第一金属板。 在第一金属板上形成电介质材料。 第二金属板以与第一金属板的至少一部分重叠以形成电介质材料的至少一个重叠区域的方式形成在电介质材料上。 重叠区域的周边的至少一部分是非平面的。 重叠区域可以形成为环形的多个部分中的大致四分之一环形的闭环形状和/或大致一半的环形形状。

公开(公告)号：US09478348B2

公开(公告)日：2016-10-25

申请号：US14313241

申请日：2014-06-24

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  David Francis Berdy ,  Jonghae Kim

IPC: H01F5/00 ,  H01F27/29 ,  H01F7/06 ,  H01F27/28 ,  H01F41/04 ,  H01F17/00 ,  H01L23/64 ,  H01L49/02 ,  H01L23/15

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/04 ,  H01F2017/002 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/15 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  Y10T29/49075 ,  H01L2924/00

Abstract: Methods and apparatuses, wherein the method forms a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height. The method forms a plurality of conductive traces external to the substrate and couples the plurality of conductive traces to the first plurality of vias: wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns and wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane.

Abstract translation: 方法和装置，其中所述方法在基底中形成第一多个通孔，还包括将所述第一多个通孔形成为基本上相同的高度。 该方法在衬底外部形成多个导电迹线，并将多个导电迹线耦合到第一多个通孔：其中多个导电迹线和第一多个通孔包括多个导电匝，并且其中多个导电 匝在基本上在第一平面内的螺旋构造。

公开(公告)号：US20160293477A1

公开(公告)日：2016-10-06

申请号：US14856418

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L21/762 ,  H01L23/29 ,  H01L23/31 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/76256 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/291 ,  H01L27/1203 ,  H01L29/78603

Abstract: Silicon-on-insulator (SOI) wafers employing molded substrates to improve insulation and reduce current leakage are provided. In one aspect, a SOI wafer comprises a substrate. An insulating layer (e.g., a buried oxide (BOX) layer) is disposed above the substrate to insulate an active semiconductor layer disposed above the insulating layer, from the substrate. Transistors are formed in the active semiconductor layer. To provide for improved insulation between the active semiconductor layer and the substrate to reduce leakage and improve performance of the active semiconductor layer, the substrate is provided in the form of a molded substrate. A coating layer is also disposed between the molded substrate and the insulating layer of the SOI wafer, in case, for example, the melting temperature of a molding compound used to form the molded substrate is not low enough to prevent contamination of the active semiconductor layer into the insulating layer.

Abstract translation: 提供了使用模制基板以提高绝缘性并减少漏电的绝缘体上硅（SOI）晶片。 在一个方面，SOI晶片包括衬底。 绝缘层（例如，掩埋氧化物（BOX）层）设置在衬底之上，以使绝缘层上方的有源半导体层与衬底绝缘。 晶体管形成在有源半导体层中。 为了提供有源半导体层和衬底之间的改善的绝缘，以减少有源半导体层的泄漏和改善性能，衬底以模制衬底的形式提供。 在模制基板和SOI晶片的绝缘层之间也设置涂层，例如，用于形成模制基板的模塑料的熔化温度不足以防止有源半导体层的污染 进入绝缘层。