公开(公告)号：US20160248149A1

公开(公告)日：2016-08-25

申请号：US14627863

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

IPC: H01Q1/36 ,  H01Q7/00

CPC classification number: H01Q1/36 ,  H01Q1/2283 ,  H01Q7/00 ,  H05K1/115 ,  H05K1/119 ,  H05K1/165 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2201/10098

Abstract: An apparatus includes a substrate package and a three dimensional (3D) antenna structure formed in the substrate package. The 3D antenna structure includes multiple substructures to enable the 3D antenna structure to operate as a beam-forming antenna. Each of the multiple substructures has a slanted-plate configuration or a slanted-loop configuration.

Abstract translation: 一种装置包括衬底封装和形成在衬底封装中的三维（3D）天线结构。 3D天线结构包括多个子结构，以使3D天线结构能够作为波束形成天线工作。 多个子结构中的每一个具有倾斜板配置或倾斜环配置。

公开(公告)号：US09425761B2

公开(公告)日：2016-08-23

申请号：US14055707

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Robert Paul Mikulka ,  Matthew Michael Nowak

IPC: H03H7/01 ,  H04B1/04

CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

Abstract translation: 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 贯通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。

公开(公告)号：US09379802B2

公开(公告)日：2016-06-28

申请号：US14684072

申请日：2015-04-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC: H04B1/06 ,  H04B1/44 ,  H03C7/02 ,  H01Q11/12 ,  H04M1/00 ,  H04B7/08 ,  H04B1/16 ,  H04B1/00 ,  H04B1/18

CPC classification number: H04B7/0805 ,  H04B1/005 ,  H04B1/16 ,  H04B1/18 ,  H04B7/0825

Abstract: A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

公开(公告)号：US09368564B2

公开(公告)日：2016-06-14

申请号：US14229317

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez

IPC: H01L21/48 ,  H01L49/02 ,  H01F17/00

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2017/002 ,  H01L21/486 ,  H01L21/4889 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/17 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract translation: 基座在支撑表面上以间距间隔开。 导电构件，可选择铜或其他金属柱，从基垫向上延伸到顶部焊盘。 顶部焊盘互连器以构造在基板之间的电感器电流路径的配置连接顶部焊盘。

公开(公告)号：US09264013B2

公开(公告)日：2016-02-16

申请号：US14019821

申请日：2013-09-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Matthew Michael Nowak

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/463 ,  H03H3/00 ,  Y10T29/4902

Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.

Abstract translation: 公开了用于减小集成电路（IC）中的磁耦合的系统。 还公开了相关的部件和方法。 IC具有多个电感器。 每个电感器产生具有可辨别轴线的磁通量。 为了减小电感器之间的磁耦合，磁通轴被设计成不平行。 特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。 这种布置可以特别适用于具有低通和高通滤波器的双工器。

公开(公告)号：US20150115403A1

公开(公告)日：2015-04-30

申请号：US14063934

申请日：2013-10-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract translation: 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。

公开(公告)号：US20150035162A1

公开(公告)日：2015-02-05

申请号：US13957462

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Mario Francisco Velez ,  Daeik D. Kim ,  David F. Berdy ,  Changhan Yun ,  Robert P. Mikulka ,  Jonghae Kim ,  Matthew M. Nowak

IPC: H01L23/522 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L23/5226 ,  G06F17/5068 ,  H01F17/0013 ,  H01F41/041 ,  H01F2017/002 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4605 ,  H01L2924/00

Abstract: An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer contacts a conductive via that extends at least partially within the substrate. The metal layer and the conductive via form at least a portion of an inductive device.

Abstract translation: 公开了一种包括导电通孔和金属层的电感器件。 形成电子器件的具体方法包括形成接触衬底表面的金属层。 包括表面的基底由基本均匀的电介质材料形成。 金属层接触至少部分地在衬底内延伸的导电通孔。 金属层和导电通孔形成电感器件的至少一部分。

公开(公告)号：US20140354372A1

公开(公告)日：2014-12-04

申请号：US14019821

申请日：2013-09-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik D. Kim ,  Mario Francisco Velez ,  Changhan Yun ,  Je-Hsiung Lan ,  Robert P. Mikulka ,  Matthew M. Nowak

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/463 ,  H03H3/00 ,  Y10T29/4902

Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.

Abstract translation: 公开了用于减小集成电路（IC）中的磁耦合的系统。 还公开了相关的部件和方法。 IC具有多个电感器。 每个电感器产生具有可辨别轴线的磁通量。 为了减小电感器之间的磁耦合，磁通轴被设计成不平行。 特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。 这种布置可以特别适用于具有低通和高通滤波器的双工器。

公开(公告)号：US20140327508A1

公开(公告)日：2014-11-06

申请号：US13887633

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Daeik D. Kim ,  Kangho Lee ,  David F. Berdy ,  Mario Francisco Velez ,  Jonghae Kim ,  Je-Hsiung Lan ,  Changhan Yun ,  Niranjan Sunil Mudakatte ,  Robert P. Mikulka

IPC: H01F29/14

CPC classification number: H01F21/06 ,  H01F21/08 ,  H01F27/255

Abstract: An inductor tunable by a variable magnetic flux density component is disclosed. A particular device includes an inductor. The device further includes a variable magnetic flux density component (VMFDC) positioned to influence a magnetic field of the inductor when a current is applied to the inductor.

Abstract translation: 公开了一种由可变磁通密度分量调节的电感器。 特定器件包括电感器。 该装置还包括可变磁通密度分量（VMFDC），其定位成当电流施加到电感器时影响电感器的磁场。

公开(公告)号：US20140197902A1

公开(公告)日：2014-07-17

申请号：US13798733

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Daeik D. Kim ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/461 ,  H01F2017/0026 ,  H01F2017/004 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/66 ,  H01L2924/0002 ,  H03H3/00 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0021 ,  H05K1/0233 ,  H05K1/0306 ,  H05K1/165 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/10098 ,  Y10T29/49128 ,  H01L2924/00

Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

Abstract translation: 双工器包括具有一组通过衬底通孔的衬底。 双工器还包括在衬底的第一表面上的第一组迹线。 第一迹线耦合到贯穿衬底通孔。 双工器还包括与第一表面相对的在衬底的第二表面上的第二组迹线。 第二迹线耦合到该组通过衬底通孔的相对端。 贯通衬底通孔和迹线也作为3D电感器工作。 双工器还包括由基板支撑的电容器。