公开(公告)号：US20040120385A1

公开(公告)日：2004-06-24

申请号：US10632566

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H04B001/707

CPC classification number: H04B1/7085 ,  G01S19/29 ,  G01S19/30 ,  H03H17/0664 ,  H04B1/70753 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，采样减速器组合接收信号的样本，以便与本地生成的GPS码版本进行相关。 在跟踪模式中，采样信号直接提供给相关器而不需要样本减少。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US20040104713A1

公开(公告)日：2004-06-03

申请号：US10620310

申请日：2003-07-14

Applicant: STMicroelectronics S.r.I.

Inventor： Adalberto Mariani ,  Giulio Corva

IPC: G05F001/40

CPC classification number: H02M3/1584

Abstract: A multiphase buck type voltage regulator having at least two phases and including a first switching means that selectively connect a supply voltage to a load through a first current path; a second switching means that selectively connect said supply voltage to said load through a second current path; a first activation circuit that activates said first switching means; a first delay circuit that deactivates said first switching means after a first period of time; a second activation circuit that activates said second switching means; a second delay circuit that after a second period of time deactivates said second switching means; said first period of time depends on said supply voltage and on the output voltage; said second period of time depends on said supply voltage and on a voltage proportional to the difference of current that flows in said first and second current path.

Abstract translation: 一种具有至少两相的多相降压式电压调节器，包括：第一开关装置，其通过第一电流路径选择性地将电源电压连接到负载; 第二开关装置，其通过第二电流路径选择性地将所述电源电压连接到所述负载; 第一激活电路，其激活所述第一开关装置; 第一延迟电路，其在第一时间段之后停用所述第一切换装置; 第二激活电路，其激活所述第二开关装置; 第二延迟电路，在第二时间段之后，使所述第二开关装置失效; 所述第一时间段取决于所述电源电压和输出电压; 所述第二时间段取决于所述电源电压和与在所述第一和第二电流路径中流动的电流差成比例的电压。

公开(公告)号：US20040061168A1

公开(公告)日：2004-04-01

申请号：US10606164

申请日：2003-06-25

Applicant: STMICROELECTRONICS S.r.I

Inventor： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

IPC: H01L029/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Abstract translation: 提供电可擦除和可编程的存储单元。 存储单元包括浮置栅极MOS晶体管和用于将电荷注入浮置栅极的双极晶体管。 浮置栅极晶体管具有形成在第一阱中的源极区和漏极区，沟道限定在漏极和源极区之间，控制栅极区以及在沟道和控制栅极区上延伸的浮动栅极。 双极晶体管具有形成在第一阱中的发射极区域，由第一阱构成的基极区域和由沟道组成的集电极区域。 存储单元包括与第一阱绝缘的第二阱，并且控制栅区形成在第二阱中。 本发明的另外的实施例提供了包括至少一个这样的存储单元的存储器，包括这种存储器的电子设备，以及集成存储器单元和擦除存储器单元的方法。

公开(公告)号：US20040039953A1

公开(公告)日：2004-02-26

申请号：US10460035

申请日：2003-06-10

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Confalonieri ,  Angelo Nagari ,  Germano Nicollini

IPC: G06F001/26 ,  G06F001/32

CPC classification number: H03K17/166 ,  H03K17/164

Abstract: A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.

Abstract translation: 数字系统包括数字数据处理单元，连接到处理单元的至少一个输出缓冲器，以响应于从处理单元到达的数字信号产生输出信号，并且至少一个用户单元作为输出缓冲器负载进行连接。 为了确保输出缓冲器的开关电流可以被设置为不同的值，输出缓冲器包括用于将开关电流固定为基本上恒定且与负载无关的值的装置和用于选择性地设置 开关电流和处理单元包括用于存储预定参数的装置; 所述装置连接到选择设定装置，用于将切换电流的值设定为预定参数的函数。

公开(公告)号：US20040031973A1

公开(公告)日：2004-02-19

申请号：US10446589

申请日：2003-05-27

Applicant: STMicroelectronics S.r.I

Inventor： Carlo Cognetti ,  Ubaldo Mastromatteo

IPC: H01L027/10

CPC classification number: H01L31/18 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2224/05099

Abstract: A process for manufacturing encapsulated optical sensors, including the steps of: forming a plurality of mutually spaced optical sensors in a wafer of semiconductor material; bonding a plate of transparent material to the wafer so as to seal the optical sensors; and dividing the wafer into a plurality of dies, each comprising an optical sensor and a respective portion of the plate.

Abstract translation: 一种用于制造封装的光学传感器的方法，包括以下步骤：在半导体材料的晶片中形成多个相互间隔的光学传感器; 将透明材料板粘合到晶片上以便密封光学传感器; 并将晶片分成多个模具，每个模具包括光学传感器和板的相应部分。

公开(公告)号：US20040019814A1

公开(公告)日：2004-01-29

申请号：US10440044

申请日：2003-05-16

Applicant: STMicroelectronics SA ,  STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Luigi Mantellassi

IPC: G06F001/26

CPC classification number: G06F9/30101 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  H01L23/34 ,  H01L2924/0002 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  H01L2924/00

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract translation: 片上系统（SoC）架构包括多个块，每个块包括功率控制模块，用于选择性地控制由该块所耗散的功率。 对于每个块，提供功率寄存器以接收功率控制指令以选择性地控制相应的功率控制模块。 该系统还包括用于将各个功率控制指令写入块的功率控制寄存器的功率控制单元，由此在功率控制单元的集中控制下，对每个块单独且独立地控制功率消耗。 对于每个块，还提供功率状态寄存器以接收关于相应块内的功率控制的状态信息。 电源控制单元从这些电源状态寄存器读取状态指令。

公开(公告)号：US20040008549A1

公开(公告)日：2004-01-15

申请号：US10440043

申请日：2003-05-15

Applicant: STMicroelectronics S.r.I

Inventor： Rino Micheloni ,  Aldo Losavio

IPC: G11C007/00

CPC classification number: G11C29/82 ,  G11C29/846

Abstract: The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in the presence of an incorrect datum. Various solutions are presented that implement column, row and sector redundancy, both in case of erasing and programming.

Abstract translation: 存储装置具有由多个标准扇区和冗余部分形成的存储块; 控制电路，其控制存储器单元的数据的编程和擦除; 以及用于存储在存储单元中的数据的正确性验证电路。 正确性验证电路由控制电路启用，并且在检测至少一个非功能单元的情况下产生不正确的基准信号。 此外，控制电路激活冗余，使冗余部分能够在存在不正确的数据的情况下将冗余数据存储在冗余存储器级中。 提出了实现列，行和扇区冗余的各种解决方案，无论在擦除和编程的情况下。

公开(公告)号：US20030235100A1

公开(公告)日：2003-12-25

申请号：US10426924

申请日：2003-04-29

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: G11C007/00

CPC classification number: G11C16/3427 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3418

Abstract: An NROM memory device, wherein the memory cells are provided with charge storage regions of insulating material, such as silicon nitride. The memory device includes a row decoder comprising a plurality of drivers; during programming, a first driver supplies a first voltage having a first value to a selected wordline, while the other drivers are configured so as to supply a second voltage having a second non-zero value, lower than the first value, to the other wordlines. Thereby, the gate-drain voltage drop of the deselected cells is reduced, and thus spurious erasing of the deselected cells connected to the selected bitline is reduced. Consequently, the reliability of the memory device is improved considerably and the life thereof is lengthened, thanks to the reduction in the charge injected into the charge storage region.

Abstract translation: 一种NROM存储器件，其中存储单元设置有诸如氮化硅的绝缘材料的电荷存储区域。 存储装置包括行解码器，其包括多个驱动器; 在编程期间，第一驱动器向所选择的字线提供具有第一值的第一电压，而其他驱动器被配置为将具有低于第一值的第二非零值的第二电压提供给其它字线 。 因此，取消选择的单元的栅极 - 漏极电压降降低，并且因此连接到所选位线的取消选择的单元的寄生擦除减少。 因此，由于注入到电荷存储区域的电荷减少，存储器件的可靠性显着提高并且寿命延长。

公开(公告)号：US20030231130A1

公开(公告)日：2003-12-18

申请号：US10172376

申请日：2002-06-14

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M001/38 ,  H03M001/10

CPC classification number: H03M1/181 ,  H03M1/468

Abstract: A method of operating an SAR-type analog-to-digital converter to match the dynamic range of an input voltage signal to be converted with the full scale range of the converter, the converter including at least one array of binary weighted capacitors. The method includes the step of obtaining a digital gain code that represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted, applying the voltage signal to be converted to the capacitor array so as to charge with the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code that have a selected binary value, and selectively coupling the capacitors of the array to one of a first and second predetermined reference voltage terminals according to an SAR technique, to obtain an output digital code corresponding to the input voltage signal.

Abstract translation: 一种操作SAR型模数转换器以匹配要转换的输入电压信号的动态范围与转换器的满量程范围的方法，所述转换器包括至少一个二进制加权电容器阵列。 该方法包括获得数字增益代码的步骤，该数字增益代码表示满量程范围和要转换的电压信号的动态范围之间的比率，将要转换的电压信号施加到电容器阵列，以便对电压进行充电 信号仅转换具有与具有选定二进制值的增益码的位相同的二进制权重的阵列电容器，并且根据SAR选择性地将阵列的电容器耦合到第一和第二预定参考电压端子之一 技术，以获得对应于输入电压信号的输出数字代码。

公开(公告)号：US20030222354A1

公开(公告)日：2003-12-04

申请号：US10406633

申请日：2003-04-02

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Paolo Ferrari

IPC: H01L029/00 ,  H01L029/40 ,  H01L021/4763 ,  H01L021/44 ,  H01L023/04 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The process for manufacturing a through insulated interconnection is performed by forming, in a body of semiconductor material, a trench extending from the front (of the body for a thickness portion thereof; filling the trench with dielectric material; thinning the body starting from the rear until the trench, so as to form an insulated region surrounded by dielectric material; and forming a conductive region extending inside said insulated region between the front and the rear of the body and having a higher conductivity than the first body. The conductive region includes a metal region extending in an opening formed inside the insulated region or of a heavily doped semiconductor region, made prior to filling of the trench.

Abstract translation: 通过绝缘互连制造的方法是通过在半导体材料体中形成从前部（其主体的厚度部分）延伸的沟槽;用电介质材料填充沟槽;从后面开始使身体变薄 直到形成由电介质材料包围的绝缘区域，形成在主体前后的绝缘区域内延伸的导电性区域，并具有比第1主体高的导电性，导电区域包括： 金属区域在形成在绝缘区域内的开口中延伸，或者在填充沟槽之前制成的重掺杂半导体区域。