公开(公告)号：US20180358476A1

公开(公告)日：2018-12-13

申请号：US15617665

申请日：2017-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L29/808 ,  H01L29/10 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/283 ,  H01L21/8232

CPC classification number: H01L29/8083 ,  H01L21/283 ,  H01L21/8232 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/66909

Abstract: A semiconductor device that is composed of an epitaxial semiconductor material stacked structure that includes a first epitaxial channel for a first junction field effect transistor (JFET) atop a supporting substrate and a second epitaxial channel region for a second junction field effect transistor (JFET). A commonly electrically contacted source/drain region for each of the first JFET and the second JFET is positioned at an interface of the first and second epitaxial channel region. A channel length for each of the first and second is substantially perpendicular to an upper surface of the supporting substrate. An epitaxial semiconductor gate conductor in direct contact with each of said first epitaxial channel region and the second epitaxial channel region.

公开(公告)号：US20180350936A1

公开(公告)日：2018-12-06

申请号：US16057324

申请日：2018-08-07

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/16 ,  H01L21/30 ,  H01L29/24 ,  H01L29/40 ,  H01L21/28

CPC classification number: H01L29/4941 ,  H01L21/02271 ,  H01L21/02592 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/3003 ,  H01L21/3065 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/16 ,  H01L29/24 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66575

Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.

公开(公告)号：US10141406B2

公开(公告)日：2018-11-27

申请号：US15823340

申请日：2017-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Keith E. Fogel ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L21/762 ,  H01L21/225 ,  H01L27/092 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/24 ,  H01L29/161 ,  H01L27/12 ,  H01L29/267

Abstract: A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins.

公开(公告)号：US10090384B2

公开(公告)日：2018-10-02

申请号：US15403856

申请日：2017-01-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Keith E. Fogel ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762

Abstract: A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins.

公开(公告)号：US20180269205A1

公开(公告)日：2018-09-20

申请号：US15907908

申请日：2018-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/07 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/739

CPC classification number: H01L27/0727 ,  G11C7/062 ,  G11C11/4091 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823487 ,  H01L29/66136 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/861

Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

公开(公告)号：US20180226415A1

公开(公告)日：2018-08-09

申请号：US15424278

申请日：2017-02-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/11507 ,  H01L27/06 ,  H01L27/092 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L27/11507 ,  H01L21/28291 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/11587 ,  H01L27/1159 ,  H01L28/55 ,  H01L28/82 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/0847

Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.

公开(公告)号：US10043825B2

公开(公告)日：2018-08-07

申请号：US15596135

申请日：2017-05-16

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L29/735 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/225 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8222

Abstract: A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions, a length of the second extrinsic base layer being different from a length of the first extrinsic base layer; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the extrinsic bases to form emitter/collector junctions; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask.

公开(公告)号：US10002924B2

公开(公告)日：2018-06-19

申请号：US14827514

申请日：2015-08-17

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/1054 ,  H01L29/0692 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of silicon fins on a substrate, wherein the plurality of silicon fins are spaced apart from each other at a pitch and formed to a height in a direction perpendicular to a top surface of the substrate, forming a nitride layer between each of adjacent silicon fins and on lateral surfaces of each of the silicon fins, removing a portion of each of the silicon fins to reduce the height of the silicon fins, epitaxially growing a silicon germanium (SiGe) layer on the remaining portion of each of the silicon fins, performing a top-down condensation process on the epitaxially grown SiGe layers to form an oxide layer and an SiGe fin under the oxide layer in place of each epitaxially grown SiGe layer and the remaining portion of each silicon fin, and removing the oxide layers and nitride layers.

公开(公告)号：US20180166563A1

公开(公告)日：2018-06-14

申请号：US15894273

申请日：2018-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L29/735 ,  H01L21/265 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/04 ,  H01L29/737 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308

Abstract: A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and patterning the germanium containing layer stopping on the crystalline oxide layer to form a base region. The method may further include forming emitter and collector extension regions on opposing sides of the base region using ion implantation, and epitaxially forming an emitter region and collector region on the crystalline oxide layer into contact with the emitter and collector extension regions. The crystalline oxide layer provides a seed layer for the epitaxial formation of the emitter and collector regions.

公开(公告)号：US09984871B2

公开(公告)日：2018-05-29

申请号：US15584898

申请日：2017-05-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/735 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/02507 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/155 ,  H01L29/165 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.