公开(公告)号：US20230261092A1

公开(公告)日：2023-08-17

申请号：US17694694

申请日：2022-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Hao-Ping Yan ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L29/7833 ,  H01L29/0607

Abstract: A fabricating method of a middle voltage transistor includes providing a substrate. A gate predetermined region is defined on the substrate. Next, a mask layer is formed to cover only part of the gate predetermined region. Then, a first ion implantation process is performed to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions. After removing the mask layer, a gate is formed to overlap the entirety gate predetermined region. Subsequently, two second lightly doping regions respectively formed within one of the first lightly doping regions. Next, two source/drain doping regions are respectively formed within one of the second lightly doping regions. Finally, two silicide layers are formed to respectively cover one of the source/drain doping regions.

公开(公告)号：US20230260930A1

公开(公告)日：2023-08-17

申请号：US17691130

申请日：2022-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  En-Chiuan Liou

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/585

Abstract: A die seal ring structure includes a metal interconnect structure on a substrate, in which the metal interconnect structure includes an inter-metal dielectric (IMD) layer on the substrate and a first metal interconnection disposed in the IMD layer. Preferably, a first side of the first metal interconnection includes a comb-shape portion in a top view, a second side of the first metal interconnection includes a linear line, a third side of the first metal interconnection includes a linear line, and a fourth side of the first metal interconnection includes a linear line.

公开(公告)号：US11721757B2

公开(公告)日：2023-08-08

申请号：US17391048

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/266 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L29/7824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/78624 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/665

Abstract: A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.

公开(公告)号：US11721702B2

公开(公告)日：2023-08-08

申请号：US17844067

申请日：2022-06-20

Applicant: United Microelectronics Corp.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Chung-Liang Chu ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L27/12 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

公开(公告)号：US11715709B2

公开(公告)日：2023-08-01

申请号：US17715067

申请日：2022-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Wen-Shen Li ,  Ching-Yang Wen

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/52 ,  H01L21/762 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/66 ,  H01L21/565 ,  H01L21/76243 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6616

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

公开(公告)号：US20230240151A1

公开(公告)日：2023-07-27

申请号：US18122730

申请日：2023-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Si-Han Tsai ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu- Ping Wang ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H10N50/20 ,  H10N50/80 ,  H10N50/01

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/20 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

公开(公告)号：US20230238058A1

公开(公告)日：2023-07-27

申请号：US17680264

申请日：2022-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen-Yang Hsueh ,  Ling-Hsiu Chou ,  Chih-Yang Hsu

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/3427 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/0483

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

公开(公告)号：US20230238043A1

公开(公告)日：2023-07-27

申请号：US18127651

申请日：2023-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10B61/10 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

公开(公告)号：US20230236553A1

公开(公告)日：2023-07-27

申请号：US17695255

申请日：2022-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei CHEN ,  Ching-Pei LIN ,  Chung-Yi CHIU ,  Te-Hsuan CHEN ,  Ming-Wei CHEN ,  Hsiao-Ying YANG

IPC: G05B13/04 ,  H01L21/66

CPC classification number: G05B13/048 ,  H01L22/14 ,  H01L22/12

Abstract: A training method of a semiconductor process prediction model, a semiconductor process prediction device, and a semiconductor process prediction method are provided. The training method of the semiconductor process prediction model includes the following steps. The semiconductor process was performed on several samples. A plurality of process data of the samples are obtained. A plurality of electrical measurement data of the samples are obtained. Some of the samples having physical defects are filtered out according to the process data. The semiconductor process prediction model is trained according to the process data and the electrical measurement data of the filtered samples.

公开(公告)号：US20230231035A1

公开(公告)日：2023-07-20

申请号：US17673819

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ta-Wei Chiu ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/8234

CPC classification number: H01L29/66704 ,  H01L29/401 ,  H01L21/823462 ,  H01L29/42364

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.