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    Memory arrays and methods of forming memory cells
    243.
    发明授权
    Memory arrays and methods of forming memory cells 有权

    公开(公告)号：US09893277B2

    公开(公告)日：2018-02-13

    申请号：US15003715

    申请日：2016-01-21

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Scott E. Sills ,  John K. Zahurak

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

    Abstract: Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.

    Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
    247.
    发明授权
    Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias 有权
    导电通孔的阵列，形成存储器阵列的方法以及形成导电通孔的方法

    公开(公告)号：US09589962B2

    公开(公告)日：2017-03-07

    申请号：US14307121

    申请日：2014-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

    IPC: H01L21/768 ,  H01L27/108 ,  H01L49/02 ,  H01L21/3213

    CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

    Abstract translation: 形成导电通孔的方法包括在衬底上垂直地形成至少三个平行线结构。 线结构单独地包括电介质顶部和电介质侧壁。 导线在垂直方向上形成并相对于线结构形成。 导线包括纵向连续部分和多个导电材料延伸部，其在紧邻的线结构之间分别向内垂直延伸。 蚀刻通过纵向连续部分垂直地进行，并且沿着导电线在间隔开的位置部分地垂直地延伸到延伸部分中，以分解纵向连续部分，以形成在紧邻线结构之间垂直延伸的单个导电通孔。 还公开了形成存储器阵列的方法。 还公开了与制造方法无关的导电通孔的阵列。

    Phase change memory structures and methods
    249.
    发明授权
    Phase change memory structures and methods 有权

    公开(公告)号：US09437816B2

    公开(公告)日：2016-09-06

    申请号：US14812284

    申请日：2015-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang

    IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

    CPC classification number: H01L45/1253 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.

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