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公开(公告)号：US11742289B2
公开(公告)日：2023-08-29
申请号：US17317510
申请日：2021-05-11
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Richard Schultz
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H01L23/532
CPC classification number: H01L23/5283 , H01L21/7682 , H01L21/76816 , H01L21/76835 , H01L23/5226 , H01L23/53295 , H01L21/76843
Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.
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公开(公告)号：US11741653B2
公开(公告)日：2023-08-29
申请号：US16941433
申请日：2020-07-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Mika Tuomi , Ruijin Wu , Anirudh R. Acharya , Kiia Kallio
CPC classification number: G06T15/005 , G06F9/3877 , G06F9/3887 , G06T17/10
Abstract: A method of tiled rendering of an image for display is provided which comprises receiving an image comprising one or more three dimensional (3D) objects and executing a visibility pass for determining locations of primitives of the image. The method also comprises executing, concurrently with the executing of the visibility pass, front end geometry processing of one of the primitives determined, from the visibility pass, to be in a first one of a plurality of tiles of the image and executing, concurrently with the executing of the visibility pass, back end processing of the one primitive in the first tile.
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公开(公告)号：US11736119B2
公开(公告)日：2023-08-22
申请号：US17722931
申请日：2022-04-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander D. Breslow , Nuwan Jayasena , John Kalamatianos
CPC classification number: H03M7/4037 , G06F3/0608 , G06F3/0661 , G06F3/0673 , G06F7/08
Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.
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公开(公告)号：US11715691B2
公开(公告)日：2023-08-01
申请号：US17323454
申请日：2021-05-18
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Milind S. Bhagavat , Rahul Agarwal , Chia-Hao Cheng
IPC: H01L23/52 , H01L23/528 , H01L23/31 , H01L23/522 , H01L23/00 , H01L21/56 , H01L25/065
CPC classification number: H01L23/5283 , H01L21/566 , H01L23/3128 , H01L23/5227 , H01L24/09 , H01L24/17 , H01L25/0655 , H01L2224/0231 , H01L2224/02373 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2924/1206 , H01L2924/1427
Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.
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公开(公告)号：US11715514B2
公开(公告)日：2023-08-01
申请号：US17359209
申请日：2021-06-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Russell J. Schreiber , John J. Wuu
IPC: G11C11/40 , G11C11/4096 , G11C11/408 , G11C7/10 , G11C11/4074 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/34
CPC classification number: G11C11/4096 , G11C7/106 , G11C7/1009 , G11C7/1087 , G11C11/4074 , G11C11/4085 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/30 , G11C16/3404
Abstract: A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.
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Patent Agency Ranking
公开(公告)号：US11709536B2
公开(公告)日：2023-07-25
申请号：US17029852
申请日：2020-09-23
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Greg Sadowski , Sriram Sundaram , Stephen Kushnir , William C. Brantley , Michael J. Schulte
Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.
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257.发明授权公开(公告)号：US11704277B2
公开(公告)日：2023-07-18
申请号：US16716390
申请日：2019-12-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Majed Valad Beigi , Yasuko Eckert , Dongping Zhang
Abstract: Systems and methods for efficiently routing qubits in a quantum computing system include selecting bubble nodes and routing qubits to the bubble nodes. The systems and methods further include dividing a system of nodes into regions and selecting a bubble node for each region. The systems and methods further include using super bubble nodes with reliable links connected to other super bubble nodes and bubble nodes to improve cross-region operations.
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公开(公告)号：US11703937B2
公开(公告)日：2023-07-18
申请号：US17483698
申请日：2021-09-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Mihir Shaileshbhai Doctor , Alexander J. Branover , Benjamin Tsien , Indrani Paul , Christopher T. Weaver , Thomas J. Gibney , Stephen V. Kosonocky , John P. Petry
IPC: G06F1/32 , G06F1/3287 , G06F1/3296 , G06F1/3234
CPC classification number: G06F1/3287 , G06F1/3265 , G06F1/3278 , G06F1/3296
Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.
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公开(公告)号：US11695897B2
公开(公告)日：2023-07-04
申请号：US17485784
申请日：2021-09-27
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Roto Le
IPC: H04N7/15 , H04N5/272 , G06T7/70 , H04L65/403 , H04N7/14
CPC classification number: H04N5/272 , G06T7/70 , H04L65/403 , H04N7/144 , H04N7/15 , G06T2207/10016 , G06T2207/30201
Abstract: Correcting engagement of a user in a video conference includes: receiving video data of a user of a participant device of a video conference; determining that one or more visual characteristics of the video data satisfy one or more criteria; and displaying, by the participant device, a visual overlay in response to the one or more criteria being satisfied.
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公开(公告)号：US11694367B2
公开(公告)日：2023-07-04
申请号：US17716186
申请日：2022-04-08
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Saurabh Sharma , Laurent Lefebvre , Sagar Shankar Bhandare , Ruijin Wu
CPC classification number: G06T9/00 , G06T1/60 , G06T2200/04
Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
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