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公开(公告)号:US09728337B2
公开(公告)日:2017-08-08
申请号:US14416978
申请日:2013-07-12
Inventor: Yann Lamy , Olivier Guiller , Sylvain Joblot
Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.
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公开(公告)号:US09712116B2
公开(公告)日:2017-07-18
申请号:US14955969
申请日:2015-12-01
Applicant: STMicroelectronics SA
Inventor: Lionel Vogt , Baudouin Martineau , Aurelien Larie
CPC classification number: H03F1/0205 , H03F1/0261 , H03F3/193 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/45179 , H03F2200/432 , H03F2200/451 , H03F2200/516 , H03F2203/21106 , H03F2203/45394
Abstract: An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying MOS transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying MOS transistors of the other amplification stages. A configuration circuit generates bias voltage for application to the bulk terminals in each amplification stage to set the threshold voltages of the amplifying MOS transistors, and thus configuring the operating range of each amplification stage so that different amplification stages have different operating ranges.
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公开(公告)号:US09710722B1
公开(公告)日:2017-07-18
申请号:US14983150
申请日:2015-12-29
Inventor: Mahesh Chandra , Antoine Drouot
CPC classification number: G06T5/20 , G06K9/4604 , G06K9/4671 , G06K9/56 , G06T5/002 , G06T11/60 , G06T2207/10016
Abstract: Various embodiments provide an optimized image filter. The optimized image and video obtains an input image and selects a target pixel for modification. Difference values are then determined between the selected target pixel and each reference pixel of a search area. Subsequently, a weighting function is used to determine weight values for each of the reference pixels of the search area based on their respective difference value. The selected target pixel is then modified by the optimized image filter using the determined weight values. A new target pixel in an apply patch is then selected for modification. The new target pixel is modified using the previously determined weight values reassigned to a new set of reference pixels. The previously determined weight values are reassigned to the new set of reference pixels based on each of the new set of reference pixels' position relative to the new target pixel.
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公开(公告)号:US20170199399A1
公开(公告)日:2017-07-13
申请号:US15468831
申请日:2017-03-24
Applicant: STMicroelectronics SA
Inventor: Jean-Robert Manouvrier
CPC classification number: G02F1/0123 , G01J9/00 , G01J9/02 , G02F1/025 , G02F1/218 , G02F1/2257 , G02F2001/212 , G02F2201/58 , G02F2203/50 , H04B10/5053 , H04B10/50575
Abstract: An optical modulator uses an optoelectronic phase comparator configured to provide, in the form of an electrical signal, a measure of a phase difference between two optical waves. The phase comparator includes an optical directional coupler having two coupled channels respectively defining two optical inputs for receiving the two optical waves to be compared. Two photodiodes are configured to respectively receive the optical output powers of the two channels of the directional coupler. An electrical circuit is configured to supply, as a measure of the optical phase shift, an electrical signal proportional to the difference between the electrical signals produced by the two photodiodes.
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公开(公告)号:US20170179196A1
公开(公告)日:2017-06-22
申请号:US15387850
申请日:2016-12-22
Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives , STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS SA
Inventor: Laurent GRENOUILLET , Sotirios Athanasiou , Philippe Galy
CPC classification number: H01L27/2454 , G11C13/0007 , G11C13/0069 , G11C2213/53 , H01L27/101 , H01L27/1207 , H01L27/2436 , H01L28/00 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/147
Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.
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公开(公告)号:US20170162672A1
公开(公告)日:2017-06-08
申请号:US15372930
申请日:2016-12-08
Applicant: Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor: Louis HUTIN , Julien BORREL , Yves MORAND , Fabrice NEMOUCHI
CPC classification number: H01L29/66643 , H01L29/0895 , H01L29/66636 , H01L29/7839
Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.
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公开(公告)号:US09648724B2
公开(公告)日:2017-05-09
申请号:US14956512
申请日:2015-12-02
Applicant: STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS SA
Inventor: Nicolas Hotellier , François Guyader , Vincent Fiori , Richard Fournel , Frédéric Gianesello
IPC: H05K1/02 , H05K1/11 , H05K1/18 , H05K3/00 , H01L21/762 , H01L21/764
CPC classification number: H05K1/0216 , H01L21/762 , H01L21/7624 , H01L21/764 , H01L24/03 , H01L24/05 , H01L29/0657 , H01L2224/02166 , H01L2224/04042 , H01L2924/00014 , H05K1/111 , H05K1/181 , H05K3/0011 , H01L2224/05599
Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.
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公开(公告)号:US09647724B2
公开(公告)日:2017-05-09
申请号:US13714151
申请日:2012-12-13
Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor: Pascal Urard , Christophe Regnier , Daniel Gloria , Olivier Hinsinger , Philippe Cavenel , Lionel Balme
CPC classification number: H04B5/0031 , G06F1/1694 , G06F1/1698 , G06F3/017 , G06F21/35 , H04B7/24 , H04L63/0869 , H04L63/18 , H04W4/008 , H04W4/80 , H04W12/06 , H04W12/08
Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.
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公开(公告)号:US20170103913A1
公开(公告)日:2017-04-13
申请号:US15129328
申请日:2015-03-27
Applicant: STMicroelectronics SA
Inventor: Didier Dutartre , Herve Jaouen
IPC: H01L21/762 , H01L21/02
CPC classification number: H01L21/7624 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02505 , H01L21/02513 , H01L21/02532 , H01L21/02595 , H01L21/763 , H01L29/04
Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
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公开(公告)号:US20170090580A1
公开(公告)日:2017-03-30
申请号:US14863493
申请日:2015-09-24
Applicant: STMICROELECTRONICS SA
Inventor: Olivier POTHIER
CPC classification number: G06F3/017 , G01S17/58 , G06F3/0325
Abstract: An electronic device includes at least one laser source configured to direct laser radiation toward a user's hand. Laser detectors are configured to receive reflected laser radiation from the user's hand. A controller is coupled to the at least one laser source and laser detectors and configured to determine a set of distance values to the user's hand for each respective laser detector and based upon a time-of-flight of the laser radiation. The controller also determines a hand gesture from among a plurality of possible hand gestures based upon the sets of distance values using Bayesian probabilities.
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