公开(公告)号：US10186322B2

公开(公告)日：2019-01-22

申请号：US15361473

申请日：2016-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C5/14 ,  G11C8/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521

Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

公开(公告)号：US20180233203A1

公开(公告)日：2018-08-16

申请号：US15952155

申请日：2018-04-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/14 ,  G11C16/28 ,  G11C8/08 ,  G11C16/08 ,  G11C16/26 ,  H01L27/112 ,  G11C16/10 ,  G11C7/06

CPC classification number: G11C16/14 ,  G11C7/065 ,  G11C8/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C2216/04 ,  H01L27/112 ,  H01L27/11582 ,  H01L28/00

Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.

公开(公告)号：US09972395B2

公开(公告)日：2018-05-15

申请号：US14875533

申请日：2015-10-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26 ,  G11C7/06 ,  G11C8/08 ,  G11C16/10 ,  G11C16/28 ,  H01L27/112

CPC classification number: G11C16/14 ,  G11C7/065 ,  G11C8/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C2216/04 ,  H01L27/112 ,  H01L27/11582 ,  H01L28/00

Abstract: The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage.

公开(公告)号：US09953719B2

公开(公告)日：2018-04-24

申请号：US15158460

申请日：2016-05-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/3431 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US20180053560A1

公开(公告)日：2018-02-22

申请号：US15479235

申请日：2017-04-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/08 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2216/04 ,  G11C2216/22

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US20180053553A1

公开(公告)日：2018-02-22

申请号：US15238681

申请日：2016-08-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2216/04 ,  G11C2216/22

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US09887206B2

公开(公告)日：2018-02-06

申请号：US15453829

申请日：2017-03-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/336 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

公开(公告)号：US09767923B2

公开(公告)日：2017-09-19

申请号：US15272417

申请日：2016-09-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC: G11C16/06 ,  G11C29/00 ,  G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  G11C29/26 ,  G11C16/04 ,  G11C16/26 ,  G11C7/04 ,  G11C29/02 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C29/76 ,  G11C5/02 ,  G11C5/06 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/26 ,  G11C2213/71 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A three-dimensional flash memory system is disclosed.

公开(公告)号：US09640263B2

公开(公告)日：2017-05-02

申请号：US14140452

申请日：2013-12-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Sakhawat M. Khan

IPC: G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/00 ,  G11C13/00

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/005 ,  G11C2211/5634

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

公开(公告)号：US09564238B1

公开(公告)日：2017-02-07

申请号：US14919005

申请日：2015-10-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Ning Bai ,  Hieu Van Tran ,  Qing Rao ,  Parviz Ghazavi ,  Kai Man Yue

IPC: G11C16/28 ,  G11C16/14

CPC classification number: G11C16/28 ,  G11C7/14 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C2216/04

Abstract: The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits. In one embodiment, when a memory cell is in read mode or erase mode, its source line is coupled to ground through a bitline of a dummy memory cell, which in turn is coupled to ground. When the memory cell is in program mode, the bitline of the dummy memory cell is coupled to an inhibit voltage, which places the dummy memory cell in a program inhibit mode that maintains the dummy memory cell in erased state.

Abstract translation: 本发明涉及使用虚拟存储单元作为源极线下拉电路的闪速存储器件。 在一个实施例中，当存储器单元处于读取模式或擦除模式时，其源极线通过虚拟存储器单元的位线耦合到地，而虚拟存储器单元进一步耦合到地。 当存储器单元处于编程模式时，虚拟存储单元的位线被耦合到禁止电压，这使得虚拟存储单元处于将虚拟存储单元维持为擦除状态的程序禁止模式。