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    Method of making embedded memory device with silicon-on-insulator substrate
    272.
    发明授权
    Method of making embedded memory device with silicon-on-insulator substrate 有权
    使用绝缘体上硅衬底制造嵌入式存储器件的方法

    公开(公告)号：US09431407B2

    公开(公告)日：2016-08-30

    申请号：US14491596

    申请日：2014-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

    IPC: H01L21/00 ,  H01L21/84 ,  H01L27/115 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/306 ,  H01L21/762 ,  H01L21/28 ,  H01L27/12

    CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

    Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

    Mixed voltage non-volatile memory integrated circuit with power saving
    274.
    发明授权
    Mixed voltage non-volatile memory integrated circuit with power saving 有权
    混合电压非易失性存储器集成电路，省电

    公开(公告)号：US09378838B2

    公开(公告)日：2016-06-28

    申请号：US14257335

    申请日：2014-04-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/04 ,  G11C16/30 ,  G11C5/14 ,  G11C16/08 ,  G11C11/56

    CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

    Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.

    Abstract translation: 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压，并由接收第一电压的电压调节器产生。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 电压调节器由控制器使能。

    Non-volatile memory cells with enhanced channel region effective width, and method of making same
    277.
    发明授权
    Non-volatile memory cells with enhanced channel region effective width, and method of making same 有权
    具有增强的通道区域有效宽度的非易失性存储单元及其制造方法

    公开(公告)号：US09293359B2

    公开(公告)日：2016-03-22

    申请号：US14191625

    申请日：2014-02-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Hieu Van Tran ,  Chien-Sheng Su ,  Prateep Tuntasood

    IPC: H01L29/788 ,  H01L21/762 ,  H01L29/66 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

    Abstract translation: 一种存储器件阵列，其具有形成在半导体衬底中的间隔开的平行隔离区域，在每对相邻隔离区域之间具有有源区域。 每个隔离区域包括形成在衬底表面中的沟槽和形成在沟槽中的绝缘材料。 绝缘材料的顶表面的部分凹陷在基底的表面下方。 每个有源区域包括一列存储单元，每个存储单元具有间隔开的第一和第二区域，其间具有通道区域，在第一沟道区域部分上的浮动栅极以及在第二沟道区域部分上的选择栅极。 选择栅极形成为垂直于隔离区域延伸的连续字线，并且每个形成用于一行存储器单元的选择栅极。 每个字线的一部分向下延伸到沟槽中并且横向设置成与沟槽的侧壁相邻。

    Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same
    280.
    发明申请
    Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same 审中-公开
    具有绝缘体硅基板的嵌入式存储器件及其制造方法

    公开(公告)号：US20150263040A1

    公开(公告)日：2015-09-17

    申请号：US14216553

    申请日：2014-03-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do

    IPC: H01L27/12 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L29/78

    CPC classification number: H01L27/1203 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7841 ,  H01L29/7881

    Abstract: A semiconductor device having a silicon substrate with a first area including a buried insulation layer with silicon over and under the insulation layer and a second area in which the substrate lacks buried insulation disposed under any silicon. Logic devices are formed in the first area having spaced apart source and drain regions formed in the silicon that is over the insulation layer, and a conductive gate formed over and insulated from a portion of the silicon that is over the insulation layer and between the source and drain regions. Memory cells are formed in the second area that include spaced apart second source and second drain regions formed in the substrate and defining a channel region therebetween, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region.

    Abstract translation: 一种具有硅衬底的半导体器件，其具有第一区域，该第一区域包括在绝缘层之上和之下的具有硅的掩埋绝缘层，以及第二区域，其中衬底缺少设置在任何硅下的掩埋绝缘体。 逻辑器件形成在第一区域中，其中形成在绝缘层之上的硅中具有间隔开的源极和漏极区域，以及形成在绝缘层之上和源极之间的硅的一部分上并与其绝缘的导电栅极 和漏区。 存储单元形成在第二区域中，该第二区域包括形成在基板中的间隔开的第二源极和第二漏极区域，并且在其间限定沟道区域;布置在沟道区域的第一部分之上并与沟道区域的第一部分绝缘的浮置栅极;以及选择栅极 并且与沟道区域的第二部分绝缘。

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