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公开(公告)号：US20240201721A1
公开(公告)日：2024-06-20
申请号：US18083229
申请日：2022-12-16
发明人： Nishant Singh THAKUR
摘要： A low dropout regulator for providing an output voltage, the low dropout regulator comprising a resistive device configured to contribute to the stability of the low dropout regulator during operation and to have a resistance that is dependent on a load current.
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公开(公告)号：US20240178317A1
公开(公告)日：2024-05-30
申请号：US18484956
申请日：2023-10-11
发明人： Takahiro MORI
IPC分类号： H01L29/78 , H01L27/088 , H01L29/06 , H01L29/10 , H01L29/66
CPC分类号： H01L29/7816 , H01L27/088 , H01L29/0692 , H01L29/1095 , H01L29/66681
摘要： In a p-type substrate region of a semiconductor substrate, an n-type source region, an n-type drain region, a p-type body region having an impurity concentration higher than an impurity concentration of the p-type substrate region, a p-type body contact region having an impurity concentration higher than the impurity concentration of the p-type body region, and an n-type drift region having an impurity concentration lower than an impurity concentration of the n-type drain region are formed. A gate electrode is formed on the semiconductor substrate via a gate dielectric film. The semiconductor substrate includes a first region and a second region that are alternately disposed in an extending direction of the gate electrode. A width of the p-type body region overlapping with the gate electrode in the second region is smaller than a width of the p-type body region overlapping with the gate electrode in the first region.
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公开(公告)号：US20240175943A1
公开(公告)日：2024-05-30
申请号：US18518327
申请日：2023-11-22
发明人： Takayuki SUZUKI
CPC分类号： G01R31/66 , G01R19/0038 , H03K5/24
摘要： A connection control circuit according to an embodiment includes an operation mode detection circuit having an operation state control circuit. In a first state in which an other device is not connected to a first device, the operation state control circuit sets the receiver circuit to an operating state and the operation mode detection circuit to a stopped state. In addition, in a second state in which the other device is connected to the first device, the operation state control circuit sets the receiver circuit to a stopped state and the operation mode detection circuit to an operating state.
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公开(公告)号：US20240170548A1
公开(公告)日：2024-05-23
申请号：US18515187
申请日：2023-11-20
发明人： Hiroya SHIMOYAMA
IPC分类号： H01L29/423 , H01L21/02 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L29/40 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/788
CPC分类号： H01L29/42328 , H01L21/02164 , H01L21/0217 , H01L21/28035 , H01L21/31111 , H01L21/32133 , H01L29/401 , H01L29/402 , H01L29/4916 , H01L29/518 , H01L29/66484 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/7831 , H01L29/7889
摘要： Provided is a semiconductor device including a field plate electrode, a floating electrode, and a gate electrode and satisfying a relationship of T1>T2>T3, where T1 is a thickness of an insulating film between the field plate electrode and an N-type drift region, T2 is a thickness of the insulating film between the floating electrode and the N-type drift region, and T3 is a thickness of the insulating film between the gate electrode and a P-type channel region.
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公开(公告)号：US20240170398A1
公开(公告)日：2024-05-23
申请号：US18511535
申请日：2023-11-16
发明人： Hiromichi TAKAOKA , Yoshiyuki SATO , Yuki FUJIMOTO
IPC分类号： H01L23/525
CPC分类号： H01L23/5256
摘要： The dielectric film IF is disposed on the semiconductor substrate SB, and the plurality of electric fuse portions FU are disposed on the dielectric film IF. The n-type first well region WL1 is disposed in the semiconductor substrate SB and on the surface of the semiconductor substrate SB. The first well region WL1 is formed by integrally connecting the well region WLa located under each of the plurality of electric fuse portions FU to each other.
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公开(公告)号：US20240170346A1
公开(公告)日：2024-05-23
申请号：US18452822
申请日：2023-08-21
发明人： Kosuke KITAICHI
CPC分类号： H01L22/14 , H01L21/78 , H01L29/402 , H01L29/66348
摘要： In a wafer test step, a dummy semiconductor element formed in a scribe region of a semiconductor substrate is inspected by using a testing electrode provided in the scribe region and electrically connected to the dummy semiconductor element. In a dicing step, the scribe region of the semiconductor substrate is cut by using a dicing blade. The testing electrode includes a plurality of pad portions and a plurality of connection portions connecting the plurality of pad portions to each other. A width of each of the plurality of connection portions is larger than a width of the dicing blade, and smaller than a width of each of the plurality of pad portions. In plan view, the plurality of pad portions is arranged in a linear manner in a moving direction of the dicing blade, and the plurality of connection portions is arranged in a staggered manner in the moving direction.
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公开(公告)号：US20240168908A1
公开(公告)日：2024-05-23
申请号：US18483711
申请日：2023-10-10
发明人： Tomoyuki NAKAMURA
摘要： A communication device includes at least one memory and at least one processor coupled to the at least one memory. The at least one processor is configured to: secure a transmission buffer that is not optionally released by a user application; monitor a storage area in which a specific field in an upper protocol header included in payload data of a frame transmitted from the transmission buffer is written; and release the transmission buffer in a case where a storage value stored in the storage area has not been updated for a certain period of time.
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28.发明授权公开(公告)号：US11990397B2
公开(公告)日：2024-05-21
申请号：US18163617
申请日：2023-02-02
发明人： Wataru Shiroi , Shuuichi Kariyazaki
IPC分类号： H01L23/498 , H01L23/00
CPC分类号： H01L23/49822 , H01L23/49816 , H01L23/49838 , H01L23/49894 , H01L24/15
摘要： A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.
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公开(公告)号：US20240164118A1
公开(公告)日：2024-05-16
申请号：US18479327
申请日：2023-10-02
CPC分类号： H10B80/00 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/16 , H01L2224/05554 , H01L2224/06155 , H01L2224/32225 , H01L2224/32265 , H01L2224/3303 , H01L2224/33181 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48108 , H01L2224/48137 , H01L2224/48145 , H01L2224/48195 , H01L2224/48229 , H01L2224/48245 , H01L2224/48265 , H01L2224/49109 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/83095 , H01L2224/92147 , H01L2924/1431 , H01L2924/1436 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106
摘要： A semiconductor device includes: a base material having a first terminal; a semiconductor chip having a first electrode pad electrically connected with the first terminal, a second electrode pad to which a power supply potential is to be supplied, and a third electrode pad to which a reference potential is to be supplied, and mounted on the base material via a first member; a chip capacitor having a first electrode and a second electrode, and mounted on the semiconductor chip via a second member; a first wire electrically connecting the first electrode pad with the first terminal; a second wire electrically connecting the second electrode pad with the first electrode without going through the base material; and a third wire electrically connecting the third electrode pad with the second electrode without going through the base material.
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公开(公告)号：US20240164112A1
公开(公告)日：2024-05-16
申请号：US18054981
申请日：2022-11-14
发明人： Ryo OGURA , Takahiro MARUYAMA
IPC分类号： H01L27/11592 , H01L27/1159
CPC分类号： H01L27/11592 , H01L27/1159
摘要： This is a manufacturing method of a semiconductor device having a first region, a second region, and a third region. A second gate dielectric film is formed on a semiconductor substrate in the second region. A thin first gate dielectric film is formed on the semiconductor substrate in the first region. A protective film is formed on the first gate dielectric film and on the second gate dielectric film. A thin paraelectric film is formed on the semiconductor substrate in the third region. An amorphous film formed of a material including a metal oxide and a first element is formed on the protective film and on the paraelectric film. A metal film is formed on the amorphous film. By performing a heat treatment, the amorphous film is crystallized to form a ferroelectric film.
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