公开(公告)号：US20080157340A1

公开(公告)日：2008-07-03

申请号：US11980498

申请日：2007-10-31

Applicant: Wen-Kun Yang ,  Chun-Hui Yu ,  Chih-wei Lin

Inventor： Wen-Kun Yang ,  Chun-Hui Yu ,  Chih-wei Lin

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L23/5389 ,  H01L23/467 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/165 ,  H01L2223/54406 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

Abstract: The present invention discloses a structure of package comprising: a substrate with die receiving through holes, conductive connecting through holes and contact metal pads; a base attached on a portion of the lower surface of the substrate; multiple dice disposed within the die receiving through holes and attached on the base; multiple dielectric layers formed on the multiple dice and the substrate; multiple re-distribution layers (RDL) formed within the multiple dielectric layers and coupled to the multiple dice; a top layer formed over the RDL; and pluralities of terminal pads formed on the backside of the substrate and coupled to the RDL through the connecting through holes. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract translation: 本发明公开了一种包装结构，其特征在于，包括：具有通孔的基板，导电连接孔和接触金属垫; 基部，其附接在所述基板的所述下表面的一部分上; 设置在模具内的多个骰子接收通孔并附接在基座上; 形成在多个骰子和基底上的多个电介质层; 在多个介电层内形成多个再分配层（RDL），并耦合到多个骰子; 在RDL上形成顶层; 以及形成在基板的背面上并通过连接通孔与RDL连接的多个端子焊盘。 RDL由包含Ti / Cu / Au合金或Ti / Cu / Ni / Au合金的合金制成。

公开(公告)号：US20070064284A1

公开(公告)日：2007-03-22

申请号：US11507086

申请日：2006-08-18

Applicant: Cheng-Kuei Chen ,  Chun-Hui Yu

Inventor： Cheng-Kuei Chen ,  Chun-Hui Yu

IPC: H04N1/04

CPC classification number: H04N1/401

Abstract: A method for position restoration. By comparing the graphic data and the restored graphic data, the graphic data closest to the restored graphic data is selected. Therefore, the graphic data scanned subsequently is correctly connected to the restored graphic data to avoid the missing line or repetition of graphic data.

Abstract translation: 一种位置恢复方法。 通过比较图形数据和恢复的图形数据，选择最接近还原图形数据的图形数据。 因此，随后扫描的图形数据正确连接到恢复的图形数据，以避免图形数据的缺失或重复。

公开(公告)号：US09583365B2

公开(公告)日：2017-02-28

申请号：US13481517

申请日：2012-05-25

Applicant: Chun Hui Yu ,  Kuo-Chung Yee ,  Chen-Hua Yu ,  Yeong-Jyh Lin ,  Chia-Hsiang Lin ,  Liang-Ju Yen ,  Lawrence Chiang Sheu

Inventor： Chun Hui Yu ,  Kuo-Chung Yee ,  Chen-Hua Yu ,  Yeong-Jyh Lin ,  Chia-Hsiang Lin ,  Liang-Ju Yen ,  Lawrence Chiang Sheu

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.

Abstract translation: 形成用于三维集成电路的互连的方法包括将金属层附接在第一载体上，将包装部件的第一侧附着在金属层上，其中该封装部件包括多个通孔。 该方法还包括使用电化学电镀工艺用金属材料填充多个通孔，其中金属层用作用于电化学电镀工艺的电极，将第二载体附着在包装部件的第二侧上，将第一 载体，在金属层上形成光致抗蚀剂层，图案化光致抗蚀剂层并分离金属层的暴露部分。

公开(公告)号：US20130313121A1

公开(公告)日：2013-11-28

申请号：US13481517

申请日：2012-05-25

Applicant: Chun Hui Yu ,  Kuo-Chung Yee ,  Chen-Hua Yu ,  Yeong-Jyh Lin ,  Chia-Hsiang Lin ,  Liang-Ju Yen ,  Lawrence Chiang Sheu

Inventor： Chun Hui Yu ,  Kuo-Chung Yee ,  Chen-Hua Yu ,  Yeong-Jyh Lin ,  Chia-Hsiang Lin ,  Liang-Ju Yen ,  Lawrence Chiang Sheu

IPC: C25D5/02 ,  C25D7/12 ,  C25D7/00

CPC classification number: H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.

Abstract translation: 形成用于三维集成电路的互连的方法包括将金属层附接在第一载体上，将包装部件的第一侧附着在金属层上，其中该封装部件包括多个通孔。 该方法还包括使用电化学电镀工艺用金属材料填充多个通孔，其中金属层用作用于电化学电镀工艺的电极，将第二载体附着在包装部件的第二侧上，将第一 载体，在金属层上形成光致抗蚀剂层，图案化光致抗蚀剂层并分离金属层的暴露部分。

公开(公告)号：US07911044B2

公开(公告)日：2011-03-22

申请号：US11647448

申请日：2006-12-29

Applicant: Wen-Kun Yang ,  Chun-Hui Yu ,  Chihwei Lin

Inventor： Wen-Kun Yang ,  Chun-Hui Yu ,  Chihwei Lin

IPC: H01L23/02

CPC classification number: H01L23/5389 ,  H01L23/467 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract translation: 本发明公开了一种包装体的结构，其特征在于，包括：具有模头的通孔的基板; 基底，其附接在所述基底的下表面上; 模具，设置在模具接收通孔内并附接在基座上; 形成在所述管芯和所述基板上的电介质层; 在所述电介质层上形成并耦合到所述管芯的再分布层（RDL）; 形成在RDL上的保护层; 以及形成在保护层上并耦合到RDL的多个焊盘。 RDL由包含Ti / Cu / Au合金或Ti / Cu / Ni / Au合金的合金制成。

公开(公告)号：US08754514B2

公开(公告)日：2014-06-17

申请号：US13206694

申请日：2011-08-10

Applicant: Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

Inventor： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC: H01L23/02 ,  H01L21/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83005

Abstract: A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

Abstract translation: 多芯片晶片级封装包括三个堆叠的半导体管芯。 第一半导体管芯被嵌入在第一光敏材料层中。 第二半导体管芯堆叠在第一半导体管芯的顶部上，其中第二半导体管芯与第一半导体管芯面对面连接。 第三半导体管芯背靠背连接到第二半导体管芯。 第二半导体管芯和第三半导体管芯都嵌入第二光敏材料层。 多芯片晶片级封装还包括形成在第一光敏材料层和第二光敏材料层中的多个通过组装通孔。

公开(公告)号：US20140070348A1

公开(公告)日：2014-03-13

申请号：US13606289

申请日：2012-09-07

Applicant: Kuo-Chung Yee ,  Chun Hui Yu

Inventor： Kuo-Chung Yee ,  Chun Hui Yu

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14632 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.

Abstract translation: 公开了使用插入器将CMOS图像传感器和图像信号处理器（ISP）集成在一起以形成封装器件模块中的系统的方法和装置。 器件模块可以包括具有衬底的插入器。 在衬底内形成插入物接触。 传感器装置可以结合到插入件的表面，其中传感器触点被结合到插入件触点的第一端。 ISP可以通过将ISP中的ISP联系人连接到插入器联系人的第二端来连接到插入器。 底层填充层可以填补插入件和ISP之间的间隙。 印刷电路板（PCB）还可以通过连接到另一插入器触点的焊球连接到插入器。 热界面材料可能与ISP和PCB接触。

公开(公告)号：US20080157341A1

公开(公告)日：2008-07-03

申请号：US11647448

申请日：2006-12-29

Applicant: Wen-Kun Yang ,  Chun-Hui Yu ,  Chihwei Lin

Inventor： Wen-Kun Yang ,  Chun-Hui Yu ,  Chihwei Lin

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L23/5389 ,  H01L23/467 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract translation: 本发明公开了一种包装体的结构，其特征在于，包括：具有模头的通孔的基板; 基底，其附接在所述基底的下表面上; 模具，设置在模具接收通孔内并附接在基座上; 形成在所述管芯和所述基板上的电介质层; 在所述电介质层上形成并耦合到所述管芯的再分布层（RDL）; 形成在RDL上的保护层; 以及形成在保护层上并耦合到RDL的多个焊盘。 RDL由包含Ti / Cu / Au合金或Ti / Cu / Ni / Au合金的合金制成。

公开(公告)号：US20080136004A1

公开(公告)日：2008-06-12

申请号：US11608404

申请日：2006-12-08

Applicant: Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

Inventor： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00012

Abstract: To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.

Abstract translation: 在第二个芯片的基座上选择和放置标准的第一个芯片尺寸封装，以获得比原始芯片尺寸封装更适合的堆叠芯片尺寸封装。 封装结构具有比传统堆叠封装尺寸更大的芯片尺寸封装。 此外，倒装芯片封装的端子引脚可以位于LGA封装的外围或BGA封装的阵列上。

公开(公告)号：US20080085572A1

公开(公告)日：2008-04-10

申请号：US11538896

申请日：2006-10-05

Applicant: Wen-Kun Yang ,  Chih-Wei Lin ,  Chun-Hui Yu

Inventor： Wen-Kun Yang ,  Chih-Wei Lin ,  Chun-Hui Yu

IPC: H01L21/60

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68354 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/09701

Abstract: The present invention discloses a semiconductor packaging method, comprises steps of back lapping a processed silicon wafer to a desired thickness. Then, the dice are separated from the processed and lapped wafer into a single die. Then, the dice are picked and placed on a tool, an active surface of the dice is attached on the tool. A molding is performed to mold the dice by molding material. The tool is then removed from the dice to form a small unit. The next step is to arrange a plurality of the small units on a carrier in a matrix from. Then, a build-up layer, a re-distribution layer are formed over the dice, followed by forming solder balls on the dice. Finally, the carrier is removed.

Abstract translation: 本发明公开了一种半导体封装方法，包括将经处理的硅晶片背面研磨成所需厚度的步骤。 然后，将骰子从经处理和研磨的晶片分离成单个模具。 然后，骰子被拾取并放置在工具上，骰子的活动表面附着在工具上。 进行模制以通过模制材料模制骰子。 然后将该工具从骰子中移除以形成小单元。 下一步是将多个小单元布置在矩阵中的载体上。 然后，在骰子上形成堆积层，再分布层，随后在骰子上形成焊球。 最后，载体被移除。