公开(公告)号：US07781878B2

公开(公告)日：2010-08-24

申请号：US12017014

申请日：2008-01-19

申请人： Yu-Ren Chen ,  Yeong-Jyh Lin

发明人： Yu-Ren Chen ,  Yeong-Jyh Lin

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49575 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A die-stacked package structure, wherein a plurality of dies are stacked on the substrate with a rotation so that a plurality of metallic ends and the metal pad on each die on the substrate can all be exposed; a plurality of metal wires are provided for electrically connecting the plurality of metal pads on the plurality of dies with the plurality metallic ends on the substrate in one wire bonding process; then an encapsulate is provided for covering the plurality of stacked dies, a plurality of metal wires and the plurality of metallic ends on the substrate.

摘要翻译： 一种管芯堆叠封装结构，其中多个管芯以旋转方式堆叠在所述衬底上，使得能够暴露所述衬底上的每个管芯上的多个金属端和所述金属焊盘; 提供多个金属线，用于在一个引线接合过程中将多个金属焊盘上的多个金属焊盘与多个金属端部电连接在基板上; 然后提供封装以覆盖多个堆叠的裸片，多个金属线以及衬底上的多个金属端。

公开(公告)号：US20130228951A1

公开(公告)日：2013-09-05

申请号：US13411293

申请日：2012-03-02

申请人： Bor-Ping Jang ,  Yeong-Jyh Lin ,  Chien Ling Hwang ,  Chung-Shi Liu

发明人： Bor-Ping Jang ,  Yeong-Jyh Lin ,  Chien Ling Hwang ,  Chung-Shi Liu

IPC分类号： B29C45/22 ,  B29C45/34

CPC分类号： H01L25/50 ,  B29C45/0046 ,  B29C45/14639 ,  B29C45/34 ,  B29C2045/0027 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.

公开(公告)号：US20070235871A1

公开(公告)日：2007-10-11

申请号：US11400182

申请日：2006-04-10

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Chiu

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Chiu

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/13 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

摘要翻译： 高频IC封装主要包括衬底，凸起芯片和多个导电填料，其中衬底具有从顶表面到底表面穿透的多个凸起孔。 芯片的有源表面以分别插入到凸块孔中的方式附接到基板的顶表面。 导电填料形成在凸起孔中，以将凸块电连接到基板的电路层。 高频IC封装具有更短的电路径和更薄的封装厚度。

公开(公告)号：US20080174000A1

公开(公告)日：2008-07-24

申请号：US12017014

申请日：2008-01-19

申请人： Yu-Ren CHEN ,  Yeong-Jyh Lin

发明人： Yu-Ren CHEN ,  Yeong-Jyh Lin

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/49575 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A die-stacked package structure, wherein a plurality of dies are stacked on the substrate with a rotation so that a plurality of metallic ends and the metal pad on each die on the substrate can all be exposed; a plurality of metal wires are provided for electrically connecting the plurality of metal pads on the plurality of dies with the plurality metallic ends on the substrate in one wire bonding process; then an encapsulate is provided for covering the plurality of stacked dies, a plurality of metal wires and the plurality of metallic ends on the substrate.

摘要翻译： 一种管芯堆叠封装结构，其中多个管芯以旋转方式堆叠在所述衬底上，使得能够暴露所述衬底上的每个管芯上的多个金属端和所述金属焊盘; 提供多个金属线，用于在一个引线接合工艺中将多个金属焊盘上的多个金属焊盘与多个金属端部电连接在基板上; 然后提供封装以覆盖多个堆叠的裸片，多个金属线以及衬底上的多个金属端。

公开(公告)号：US20080124828A1

公开(公告)日：2008-05-29

申请号：US11601753

申请日：2006-11-20

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Shu-Ching Ho ,  Yi-Chang Lee ,  Yeong-Jyh Lin

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Shu-Ching Ho ,  Yi-Chang Lee ,  Yeong-Jyh Lin

IPC分类号： H01L21/56

CPC分类号： G01R1/06744 ,  G01R3/00

摘要： MEMS processes for fabrication of a MEMS alloy probe are revealed. Multiple layers of the MEMS alloy probe are formed on the substrate in sequences as a first surface layer, a first conductive layer, a core layer, a second conductive layer, and a second surface layer where the width of the first conductive layer is smaller than the one of first surface layer so that all the exposed edges of the first surface layer are not covered by the first conductive layer. The second surface layer is extended from the sidewalls of the core layer to the exposed edges of the first surface layer to encapsulate the core layer, the first conductive layer, and the second conductive layer. The MEMS alloy probe fabricated by the MEMS processes can eliminate the issue of oxidation.

摘要翻译： 揭示了用于制造MEMS合金探针的MEMS工艺。 多层MEMS合金探针以顺序形成在基板上，作为第一表面层，第一导电层，芯层，第二导电层和第二表面层，其中第一导电层的宽度小于 第一表面层中的一个，使得第一表面层的所有暴露边缘都不被第一导电层覆盖。 第二表面层从芯层的侧壁延伸到第一表面层的暴露边缘，以封装芯层，第一导电层和第二导电层。 通过MEMS工艺制造的MEMS合金探针可以消除氧化问题。

公开(公告)号：US09583365B2

公开(公告)日：2017-02-28

申请号：US13481517

申请日：2012-05-25

申请人： Chun Hui Yu ,  Kuo-Chung Yee ,  Chen-Hua Yu ,  Yeong-Jyh Lin ,  Chia-Hsiang Lin ,  Liang-Ju Yen ,  Lawrence Chiang Sheu

发明人： Chun Hui Yu ,  Kuo-Chung Yee ,  Chen-Hua Yu ,  Yeong-Jyh Lin ,  Chia-Hsiang Lin ,  Liang-Ju Yen ,  Lawrence Chiang Sheu

IPC分类号： H01L21/48 ,  H01L23/498

CPC分类号： H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.

摘要翻译： 形成用于三维集成电路的互连的方法包括将金属层附接在第一载体上，将包装部件的第一侧附着在金属层上，其中该封装部件包括多个通孔。 该方法还包括使用电化学电镀工艺用金属材料填充多个通孔，其中金属层用作用于电化学电镀工艺的电极，将第二载体附着在包装部件的第二侧上，将第一 载体，在金属层上形成光致抗蚀剂层，图案化光致抗蚀剂层并分离金属层的暴露部分。

公开(公告)号：US09021682B2

公开(公告)日：2015-05-05

申请号：US13527459

申请日：2012-06-19

申请人： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Yi-Li Hsiao ,  Ming-Da Cheng ,  Tsai-Tsung Tsai ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Yi-Li Hsiao ,  Ming-Da Cheng ,  Tsai-Tsung Tsai ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： H01R43/052 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L21/4853 ,  H01L24/13 ,  H01L24/78 ,  H01L2224/056 ,  H01L2224/1111 ,  H01L2224/1134 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48 ,  H01L2224/7855 ,  H01L2224/78621 ,  H01L2224/85051 ,  H01L2224/854 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/206 ,  Y10T29/49192 ,  Y10T29/49213 ,  Y10T29/514 ,  Y10T29/5177 ,  Y10T29/53217 ,  Y10T29/53235 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01049 ,  H01L2224/4554

摘要： An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.

摘要翻译： 一种装置包括：线圈，其被配置为供应线，被配置为在所述线中形成切口的切割装置，以及被配置为结合所述线并形成柱形凸块的毛细管。 该设备还被配置为拉动线在凹口处断裂，尾部区域附接到柱形凸块。

公开(公告)号：US20130313121A1

公开(公告)日：2013-11-28

申请号：US13481517

申请日：2012-05-25

申请人： Chun Hui Yu ,  Kuo-Chung Yee ,  Chen-Hua Yu ,  Yeong-Jyh Lin ,  Chia-Hsiang Lin ,  Liang-Ju Yen ,  Lawrence Chiang Sheu

发明人： Chun Hui Yu ,  Kuo-Chung Yee ,  Chen-Hua Yu ,  Yeong-Jyh Lin ,  Chia-Hsiang Lin ,  Liang-Ju Yen ,  Lawrence Chiang Sheu

IPC分类号： C25D5/02 ,  C25D7/12 ,  C25D7/00

CPC分类号： H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.

摘要翻译： 形成用于三维集成电路的互连的方法包括将金属层附接在第一载体上，将包装部件的第一侧附着在金属层上，其中该封装部件包括多个通孔。 该方法还包括使用电化学电镀工艺用金属材料填充多个通孔，其中金属层用作用于电化学电镀工艺的电极，将第二载体附着在包装部件的第二侧上，将第一 载体，在金属层上形成光致抗蚀剂层，图案化光致抗蚀剂层并分离金属层的暴露部分。

公开(公告)号：US08540136B1

公开(公告)日：2013-09-24

申请号：US13605403

申请日：2012-09-06

申请人： Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien Ling Hwang ,  Yi-Li Hsiao ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien Ling Hwang ,  Yi-Li Hsiao ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： B23K31/02 ,  B23K37/00

CPC分类号： B23K31/02 ,  B21D53/36 ,  B23K20/007 ,  H01L2224/78301 ,  Y10T29/49

摘要： Methods for forming stud bumps and apparatuses for forming stud bumps are disclosed. According to an embodiment, a method includes clamping a wire with a clamp. The clamp includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method further includes bonding the wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface. The second notch is the notch pitch distance from the first notch along the wire.

摘要翻译： 公开了用于形成柱形凸块的方法和用于形成凸块凸块的装置。 根据实施例，一种方法包括用夹具夹紧线。 所述夹具包括至少两个相对的板，并且当所述线被夹紧形成所述线中的第一凹口时，所述相对板中的至少一个包括与所述线相交的突出特征。 该方法还包括将线接合到接合表面，将线从夹具中释放出来，使线穿过钳口的间距距离通过夹具夹紧线，夹具在线中形成第二凹口，并将线断开， 接合表面上的导线的接合部分。 第二个凹口是距离第一个凹口沿导线的切口间距距离。

公开(公告)号：US20070262439A1

公开(公告)日：2007-11-15

申请号：US11583951

申请日：2006-10-20

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49572 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.

摘要翻译： 一种用于增强嵌入式凸块的结合性的IC封装，主要包括具有多个凸块容纳孔，凸起芯片，密封剂和多个外部端子的基板。 基板还分别在凸块容纳孔的一​​端具有多个内垫。 内部焊盘可以是啮合的，或者在其上设置焊接层以改善凸块连接。 芯片被附接到基板上，凸块对准并嵌入在相应的凸起容纳孔中。 密封剂至少形成在基底的下表面上以封装网眼或焊接层。 通过悬挂的网格或/和焊接层，可以在较低的温度下容易地接合凸块，以简化具有更短导电路径和更薄的封装形状的制造工艺，而无需扫线。