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公开(公告)号：US06190973B1
公开(公告)日：2001-02-20
申请号：US09215797
申请日：1998-12-18
IPC分类号： H01L218234
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28273 , H01L29/42368 , H01L29/518
摘要： The present invention provides a method of forming a high quality thin oxide on a semiconductor body. A sacrificial oxide is formed on the semiconductor and then etched to eliminate the surface contamination of the semiconductor body. Then, an EEPROM oxide is formed following by an arsenic implant. Next the EEPROM oxide on the semiconductor body is then prepared by thin oxide growth. The thin oxide is preferably formed in a steam ambient. Subsequently, the oxide is annealed under nitrous oxide ambient using a combination of in-situ and RTP annealing process.
摘要翻译： 本发明提供了在半导体本体上形成高品质薄氧化物的方法。 在半导体上形成牺牲氧化物，然后蚀刻以消除半导体本体的表面污染。 然后，通过砷注入形成EEPROM氧化物。 接下来，通过薄氧化物生长制备半导体本体上的EEPROM氧化物。 薄氧化物优选在蒸汽环境中形成。 随后，使用原位和RTP退火工艺的组合，氧化物在一氧化二氮环境下进行退火。
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公开(公告)号：US09249498B2
公开(公告)日：2016-02-02
申请号：US12825091
申请日：2010-06-28
CPC分类号： H01J37/3467 , C23C14/08 , C23C14/082 , C23C14/088 , C23C14/3407 , C23C14/3485 , C23C14/35 , H01J37/3417 , H01J37/3426 , H01J2237/3322 , H01L21/02192 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less.
摘要翻译： 本文描述了使用高功率脉冲磁控溅射的存储器。 一个或多个方法实施例包括在使用高功率脉冲磁控溅射（HIPIMS）的结构上形成电阻式存储器材料，其中在具有大约400摄氏度或更低的温度的环境中在该结构上形成电阻性存储材料。
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公开(公告)号：US20120267599A1
公开(公告)日：2012-10-25
申请号：US13517747
申请日：2012-06-14
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625 , H01L45/1633
摘要： The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.
摘要翻译： 本公开包括高密度电阻随机存取存储器（RRAM）装置，以及制造高密度RRAM装置的方法。 形成RRAM器件的一种方法包括形成具有金属 - 金属氧化物界面的电阻元件。 形成电阻元件包括在第一电极上形成绝缘材料，以及在绝缘材料中形成通孔。 通孔由金属材料共形填充，并且金属材料被平坦化到通孔内。 通孔内的金属材料的一部分被选择性地处理以在通孔内产生金属 - 金属氧化物界面。 第二电极形成在电阻元件上。
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公开(公告)号：US07919829B2
公开(公告)日：2011-04-05
申请号：US11846427
申请日：2007-08-28
IPC分类号： H01L29/00
CPC分类号： H01L21/76224 , H01L21/76227
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.
摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面蚀刻沟槽之后，将氮化硅屏障沉积到沟槽中。 氮化硅层在沟壁附近具有高氮含量以保护壁。 进一步从沟槽壁的氮化硅层具有低的氮含量和高的硅含量，以提高粘附性。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体。 所得的沟槽具有良好粘附的绝缘体，其有助于沟槽的绝缘性能。
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25.发明申请公开(公告)号：US20100013107A1
公开(公告)日：2010-01-21
申请号：US12174393
申请日：2008-07-16
申请人： Gurtej S. Sandhu , Nishant Sinha , John A. Smythe
发明人： Gurtej S. Sandhu , Nishant Sinha , John A. Smythe
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5283 , H01L21/76805 , H01L21/76816 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/53209 , H01L23/5329 , H01L25/0657 , H01L25/50 , H01L27/105 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.
摘要翻译： 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。 还公开了形成包括至少一个互连结构的半导体器件的方法。
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公开(公告)号：US20090269569A1
公开(公告)日：2009-10-29
申请号：US12497791
申请日：2009-07-06
申请人： Janos Fucsko , John A. Smythe, III , Li Li , Grady S. Waldo
发明人： Janos Fucsko , John A. Smythe, III , Li Li , Grady S. Waldo
CPC分类号： H01L21/02164 , H01L21/02222 , H01L21/02236 , H01L21/02282 , H01L21/02343 , H01L21/3125 , H01L21/316 , H01L21/76205 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832
摘要： Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.
摘要翻译： 公开了利用聚硅氮烷基氧化硅层或填充物的半导体器件，结构和系统以及制造氧化物层的方法。 在一个实施方案中，将聚硅氮烷溶液沉积在基底上，并在低温下经湿氧化处理臭氧，以将聚硅氮烷材料化学改性为氧化硅层。
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公开(公告)号：US07514366B2
公开(公告)日：2009-04-07
申请号：US11470150
申请日：2006-09-05
IPC分类号： H01L21/311
CPC分类号： H01L21/76224 , H01L21/76227
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.
摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面蚀刻沟槽之后，将氮化硅屏障沉积到沟槽中。 氮化硅层在沟壁附近具有高氮含量以保护壁。 进一步从沟槽壁的氮化硅层具有低的氮含量和高的硅含量，以提高粘附性。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体。 所得的沟槽具有良好粘附的绝缘体，其有助于沟槽的绝缘性能。
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28.发明授权Method of forming an isolation structure that includes forming a silicon layer at a base of the recess 有权形成隔离结构的方法，包括在凹部的基部形成硅层公开(公告)号：US07479440B2
公开(公告)日：2009-01-20
申请号：US11622374
申请日：2007-01-11
申请人： John A. Smythe, III , William Budge
发明人： John A. Smythe, III , William Budge
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.
摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，衬垫层优选沉积到沟槽中。 然后在沟槽上进行各向异性等离子体处理。 在等离子体工艺期间，硅层可以沉积在沟槽的基底上，或等离子体可以处理衬层。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体，并且氧化沟槽底部的富硅层。 所得到的沟槽具有从沟槽的顶部到底部的一致的蚀刻速率。
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公开(公告)号：US20080085612A1
公开(公告)日：2008-04-10
申请号：US11543515
申请日：2006-10-05
申请人： John A. Smythe , Gurtej S. Sandhu , Brian J. Coppa , Shyam Surthi , Shuang Meng
发明人： John A. Smythe , Gurtej S. Sandhu , Brian J. Coppa , Shyam Surthi , Shuang Meng
IPC分类号： H01L21/469
CPC分类号： H01L21/3088 , H01L21/02164 , H01L21/02211 , H01L21/0228 , H01L21/3086 , H01L21/3141 , H01L21/31612
摘要： Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
摘要翻译： 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。
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公开(公告)号：US08575040B2
公开(公告)日：2013-11-05
申请号：US12497791
申请日：2009-07-06
申请人： Janos Fucsko , John A. Smythe, III , Li Li , Grady S. Waldo
发明人： Janos Fucsko , John A. Smythe, III , Li Li , Grady S. Waldo
IPC分类号： H01L21/76
CPC分类号： H01L21/02164 , H01L21/02222 , H01L21/02236 , H01L21/02282 , H01L21/02343 , H01L21/3125 , H01L21/316 , H01L21/76205 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832
摘要： Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.
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