公开(公告)号：US20070114641A1

公开(公告)日：2007-05-24

申请号：US11602098

申请日：2006-11-20

Applicant: Kim-yong Goh ,  Tong-yan Tee

Inventor： Kim-yong Goh ,  Tong-yan Tee

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract translation: 一种超薄四边形扁平无铅（QFN）半导体芯片封装，其具有引线框架，该引线框架具有由顶部和底部表面的凹部形成的引线端子和形成在顶部或底部表面上的基本上对准的接触区域。 模具电连接到多个引线端子，并且模制化合物将引线框封装在一起，以形成超薄QFN封装。 因此，基本对准的接触区域暴露在封装的顶表面和底表面上。 本公开还提供了一种超薄光学四方扁平无引线（OQFN）半导体芯片封装，包括至少两个QFN半导体芯片封装的堆叠半导体模块，以及用于制造超薄四面体扁平无铅 QFN）半导体封装。

公开(公告)号：US08642396B2

公开(公告)日：2014-02-04

申请号：US13196641

申请日：2011-08-02

Applicant: Kim-yong Goh ,  Tong-yan Tee

Inventor： Kim-yong Goh ,  Tong-yan Tee

IPC: H01L21/44

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract translation: 一种超薄四边形扁平无铅（QFN）半导体芯片封装，其具有引线框架，该引线框架具有由顶部和底部表面的凹部形成的引线端子和形成在顶部或底部表面上的基本上对准的接触区域。 模具电连接到多个引线端子，并且模制化合物将引线框封装在一起，以形成超薄QFN封装。 因此，基本对准的接触区域暴露在封装的顶表面和底表面上。 本公开还提供了一种超薄光学四方扁平无引线（OQFN）半导体芯片封装，包括至少两个QFN半导体芯片封装的堆叠半导体模块，以及用于制造超薄四面体扁平无铅 QFN）半导体封装。

公开(公告)号：US08637352B2

公开(公告)日：2014-01-28

申请号：US13302602

申请日：2011-11-22

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L21/00

CPC classification number: H01L24/97 ,  B23K1/0016 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package.

Abstract translation: 提供球栅阵列引脚网格阵列转换方法。 示例性方法可以包括将多个焊球耦合到相应的多个引脚栅极阵列接触焊盘。 多个焊球中的每一个被封装在固定材料中。 多个焊球的一部分和固定材料的一部分被去除以提供多个暴露的焊球。 暴露的焊球被软化，并且多个销构件中的每一个插入软化的暴露的焊球中。 多个销构件形成销栅格阵列封装。

公开(公告)号：US08436255B2

公开(公告)日：2013-05-07

申请号：US12651295

申请日：2009-12-31

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H05K1/11

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/293 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L2224/03334 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05571 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/221 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80815 ,  H01L2224/814 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3025 ,  Y10T29/49117 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit.

Abstract translation: 包含电子封装中的球栅阵列的焊料元件的聚合物层。 聚合物层通过将球栅阵列的元件包围在粘合到封装结构的刚性聚合物层中来加强焊球组分界面处的焊料接合。 通过球栅阵列施加到封装的应力通过聚合物层传递到封装结构，绕过焊点并改善机电电路的可靠性。 在制造聚合物层的方法的一个实施方案中，与封装结构上的外部焊盘接合的焊料元素浸没在聚合物层的流体形式中。 流体形式被固化，然后去除所得聚合物层的一部分，以使焊料元件可接近以将封装安装到印刷电路板或其它外部电路。

公开(公告)号：US20130093072A1

公开(公告)日：2013-04-18

申请号：US13273027

申请日：2011-10-13

Applicant: Xueren Zhang ,  Wingshenq Wong ,  Kim-Yong Goh ,  Yiyi Ma

Inventor： Xueren Zhang ,  Wingshenq Wong ,  Kim-Yong Goh ,  Yiyi Ma

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/49513 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00

Abstract: A leadframe includes a die pad and a protective wall surrounding the die pad. A semiconductor die is situated on the die pad. Indentations are formed on the four inner corners of the protective wall adjacent the corners of the semiconductor die.

Abstract translation: 引线框架包括芯片焊盘和围绕芯片焊盘的保护壁。 半导体管芯位于管芯焊盘上。 在与半导体管芯的角部相邻的保护壁的四个内角上形成有凹痕。

公开(公告)号：US08410598B2

公开(公告)日：2013-04-02

申请号：US12982722

申请日：2010-12-30

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L23/34 ,  H01L21/60 ,  H01L21/56

CPC classification number: H01L23/13 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Abstract translation: 形成半导体封装，其具有并置在半导体管芯的至少两侧上的衬底。 衬底和半导体管芯都被固定到导电层，该导电层将半导体封装的使用期间产生的热量从半导体管芯和衬底拉出。 还存在固定到基板和半导体管芯上的电触点。 电触点促进半导体管芯，衬底和利用半导体管芯的任何外部器件或器件之间的电连接。 衬底，半导体管芯和一些电触点的至少一部分被封装在绝缘元件的封装层上。 没有被封装层包围的电触点的部分固定在诸如印刷电路板的外部装置上。

公开(公告)号：US08389335B2

公开(公告)日：2013-03-05

申请号：US13424610

申请日：2012-03-20

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L21/00

CPC classification number: H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract translation: 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。

公开(公告)号：US20120168929A1

公开(公告)日：2012-07-05

申请号：US12982722

申请日：2010-12-30

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L23/34 ,  H01L21/60 ,  H01L21/56

CPC classification number: H01L23/13 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Abstract translation: 形成半导体封装，其具有并置在半导体管芯的至少两侧上的衬底。 衬底和半导体管芯都固定到导电层，该导电层将半导体封装的使用期间产生的热量从半导体管芯和衬底上吸取。 还存在固定到基板和半导体管芯上的电触点。 电触点促进半导体管芯，衬底和利用半导体管芯的任何外部器件或器件之间的电连接。 衬底，半导体管芯和一些电触点的至少一部分被封装在绝缘元件的封装层上。 没有被封装层包围的电触点的部分固定在诸如印刷电路板的外部装置上。

公开(公告)号：US08164179B2

公开(公告)日：2012-04-24

申请号：US12336422

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/12

CPC classification number: H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract translation: 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。

公开(公告)号：US20110156250A1

公开(公告)日：2011-06-30

申请号：US12651365

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L21/565 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto.

Abstract translation: 用于封装封装应用的倒装芯片扇出晶片级封装包括在倒装芯片配置的上表面上具有焊料凸块的半导体管芯。 模具倒置，上表面面向再分布层的上侧，焊料凸块与再分布层的相应芯片接触焊盘电接触。 再分配层包括导电迹线，其将每个焊料凸点与多个上再分布接触焊盘和多个下再分布接触焊盘之一中的一个或两者电接触。 多个上再分配接触垫中的每一个具有与其接触的上焊球。 模具和上焊球至少部分地封装在位于再分配层的上表面上的模具化合物层中，并且其横向尺寸由再分布层的横向尺寸限定。 模具化合物层具有背面表面，每个上焊球的一部分暴露在其中，用于与上封装电接触。 每个下再分布接触垫具有与其耦合的较低焊球。