Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method
    21.
    发明授权
    Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method 有权
    绝缘体上硅(SOI)结构配置为减少谐波,设计结构和方法

    公开(公告)号:US08698244B2

    公开(公告)日:2014-04-15

    申请号:US12634893

    申请日:2009-12-10

    IPC分类号: H01L27/12

    摘要: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

    摘要翻译: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂,使得其具有相对高的电阻率。 此外,与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量,具有相同导电类型的不同掺杂剂或其组合。 任选地,在该相同部分内形成微腔,以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压(Vt),从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD
    24.
    发明申请
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 有权
    用于减少谐波的硅绝缘体(SOI)结构,设计结构和方法

    公开(公告)号:US20110131542A1

    公开(公告)日:2011-06-02

    申请号:US12634893

    申请日:2009-12-10

    IPC分类号: G06F17/50

    摘要: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

    摘要翻译: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂,使得其具有相对高的电阻率。 此外,与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量,具有相同导电类型的不同掺杂剂或其组合。 任选地,在该相同部分内形成微腔,以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压(Vt),从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

    Merged Field Effect Transistor Cells For Switching
    25.
    发明申请
    Merged Field Effect Transistor Cells For Switching 失效
    合并场效应晶体管电池用于开关

    公开(公告)号:US20090224334A1

    公开(公告)日:2009-09-10

    申请号:US12045159

    申请日:2008-03-10

    CPC分类号: H01L27/1203 H01L27/0705

    摘要: Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and essentially symmetrical relative to an adjacent set. Arranging the sets in this manner allows adjacent diffusion regions of the same type (i.e., sources or drains) from adjacent sets to be merged. Merging of the diffusion regions provides several benefits, including but not limited to, reducing the device size, reducing the amount of required wiring for the device (i.e., reducing resistance) and reducing side capacitance between the now merged diffusion regions and the substrate. Also disclosed are embodiments of an associated design structure for the device and an associated method of forming the device.

    摘要翻译: 公开了一种改进的集成电路开关装置的实施例,其包括多组串联连接的场效应晶体管,每组集合进一步在两个节点之间并联连接。 这些组以线性方式布置,其中每组被定位成使得其相对于相邻组接触并且基本上对称。 以这种方式布置集合允许相邻集合的相邻类型(即,源或漏极)的相邻扩散区域被合并。 扩散区域的合并提供了几个好处,包括但不限于减小器件尺寸,减少器件所需的布线的量(即降低电阻)并减小现在合并的扩散区域和衬底之间的侧电容。 还公开了用于装置的相关联的设计结构的实施例以及形成装置的相关联的方法。

    FASTENER FOR A CONNECTOR IN AN ELECTRICAL COUPLING
    26.
    发明申请
    FASTENER FOR A CONNECTOR IN AN ELECTRICAL COUPLING 审中-公开
    紧固件用于电气连接中的连接器

    公开(公告)号:US20160104951A1

    公开(公告)日:2016-04-14

    申请号:US14514316

    申请日:2014-10-14

    IPC分类号: H01R4/30

    CPC分类号: H01R4/30 H01R4/366

    摘要: A fastener for a connector in an electrical coupling including a threaded bolt, a keeper member and a biasing member. The keeper member having a base and a distal member spaced apart from each other and a collapsible portion coupling the base and the distal member to each other in electrical communication. The second end of the threaded bolt extends to the base and is in electrical communication therewith. The distal member has a conductor contact surface. The biasing member includes an inner washer, an outer washer, and a Belleville washer positioned therebetween. The biasing member is insertable between the base and the distal member so that the inner washer is positioned between the base and the Belleville washer and the outer washer is positioned between the Belleville washer and the distal member. The collapsible portion provides an electrical shunt around the biasing member.

    摘要翻译: 一种用于在电耦合中的连接器的紧固件,包括螺栓,保持构件和偏置构件。 保持器构件具有彼此间隔开的基部和远端构件以及将基部和远端构件彼此电连接的可收缩部分。 螺纹螺栓的第二端延伸到基座并与其电连通。 远端构件具有导体接触表面。 偏置构件包括内垫圈,外垫圈和位于其间的Belleville垫圈。 偏置构件可插入到基座和远端构件之间,使得内垫圈定位在基座和贝氏垫圈之间,而外垫圈位于Belleville垫圈和远端构件之间。 可折叠部分围绕偏置构件提供电分流。