公开(公告)号：US20070158861A1

公开(公告)日：2007-07-12

申请号：US11713362

申请日：2007-03-01

Applicant: Chien-Ping Huang ,  Yu-Po Wang

Inventor： Chien-Ping Huang ,  Yu-Po Wang

IPC: H01L23/28

CPC classification number: H01L24/10 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.

Abstract translation: 提供了一种形成在芯片上的积层的半导体封装以及半导体封装的制造方法。 在其接合焊盘上形成有多个导电凸块的芯片被容纳在载体的空腔内，并且介电层封装其端部露出的导电凸块。 多个导电迹线形成在电介质层上并与导电凸块的端部电连接。 焊接掩模层施加在导电迹线上并形成有开口，通过该开口，导电迹线的预定部分暴露并结合到多个焊球。 因此，接合焊盘的位置容易地被导电凸块的露出端识别和区分，使得导电迹线能够通过导电凸块与接合焊盘良好地电连接，以提高制造的封装的产量。

公开(公告)号：US20070096336A1

公开(公告)日：2007-05-03

申请号：US11411740

申请日：2006-04-25

Applicant: Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/83951 ,  H01L2224/92125 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.

Abstract translation: 提供半导体封装及其基板结构。 施加在基板结构上的焊接掩模层形成有对应于基板结构的芯片安装区域的角部的向外延伸的开口。 当倒装芯片半导体芯片安装在芯片安装区域并执行底部填充工艺时，底部填充材料可以填充倒装芯片半导体芯片和基板结构之间的间隙，并且有效地填充焊料的向外延伸的开口 掩模层对应于芯片安装区域的角部，以便为倒装芯片半导体芯片的拐角提供足够的保护，并防止在随后的热循环期间倒装芯片半导体芯片的拐角处的分层。

公开(公告)号：US07629199B2

公开(公告)日：2009-12-08

申请号：US11713362

申请日：2007-03-01

Applicant: Chien-Ping Huang ,  Yu-Po Wang

Inventor： Chien-Ping Huang ,  Yu-Po Wang

IPC: H01L21/00

CPC classification number: H01L24/10 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.

Abstract translation: 提供了一种形成在芯片上的积层的半导体封装以及半导体封装的制造方法。 在其接合焊盘上形成有多个导电凸块的芯片被容纳在载体的空腔内，并且介电层封装其端部露出的导电凸块。 多个导电迹线形成在电介质层上并与导电凸块的端部电连接。 焊接掩模层施加在导电迹线上并形成有开口，通过该开口，导电迹线的预定部分暴露并结合到多个焊球。 因此，接合焊盘的位置容易地被导电凸块的露出端识别和区分，使得导电迹线能够通过导电凸块与接合焊盘良好地电连接，以提高制造的封装的产量。

公开(公告)号：US07271493B2

公开(公告)日：2007-09-18

申请号：US11112108

申请日：2005-04-21

Applicant: Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L29/40

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20070164386A1

公开(公告)日：2007-07-19

申请号：US11648045

申请日：2006-12-28

Applicant: Cheng-Yi Chang ,  Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

Inventor： Cheng-Yi Chang ,  Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

IPC: H01L31/0203 ,  H01L21/56

CPC classification number: H01L27/14687 ,  H01L24/97 ,  H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2224/85 ,  H01L2924/00014

Abstract: A semiconductor device and the fabrication method thereof are provided. The fabrication method includes providing a substrate module plate having a plurality of substrates; attaching at least one sensor chip to each of the substrates of the substrate module plate; electrically connecting each of the sensor chips to each of the substrates through bonding wires; forming an insulating layer between each sensor chip on the substrate module plate, wherein the height of the insulating layers are not greater than the thickness of the sensor chips so as to prevent flash from the insulating layers from contaminating the sensor chips; forming an adhesive lip on the insulating layer or forming a second insulating layer followed by forming the adhesive layer, wherein the adhesive layer or the second insulating layer is higher than the highest loop-height of the bonding wires; adhering a light transmitting cover to each adhesive layer to cover the sensor chip; and cutting the substrate module plate to separate the substrates to form a plurality of semiconductor devices each integrated with at least one sensor chip. As the adhesive layers are not in contact with the bonding wires, the problems of damaging or breaking the bonding wires can be prevented in the process of adhering the light transmitting cover.

Abstract translation: 提供半导体器件及其制造方法。 该制造方法包括提供具有多个基板的基板模块板; 将至少一个传感器芯片附接到所述基板模块板的每个基板; 通过接合线将每个传感器芯片电连接到每个基板; 在衬底模块板上的每个传感器芯片之间形成绝缘层，其中绝缘层的高度不大于传感器芯片的厚度，以防止来自绝缘层的闪光污染传感器芯片; 在所述绝缘层上形成粘合剂唇缘或形成第二绝缘层，接着形成所述粘合剂层，其中所述粘合剂层或所述第二绝缘层高于所述接合线的最高环高度; 将透光盖粘附到每个粘合剂层以覆盖传感器芯片; 以及切割所述基板模块板以分离所述基板以形成多个半导体器件，每个半导体器件与至少一个传感器芯片集成。 由于粘合层不与接合线接触，所以在粘接透光罩的过程中可以防止损坏或断裂接合线的问题。

公开(公告)号：US20050258537A1

公开(公告)日：2005-11-24

申请号：US10632709

申请日：2003-07-31

Applicant: Chien-Ping Huang ,  Yu-Po Wang

Inventor： Chien-Ping Huang ,  Yu-Po Wang

IPC: H01L21/48 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/10 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.

Abstract translation: 提供了一种形成在芯片上的积层的半导体封装以及半导体封装的制造方法。 在其接合焊盘上形成有多个导电凸块的芯片被容纳在载体的空腔内，并且介电层封装其端部露出的导电凸块。 多个导电迹线形成在电介质层上并与导电凸块的端部电连接。 焊接掩模层施加在导电迹线上并形成有开口，通过该开口，导电迹线的预定部分暴露并结合到多个焊球。 因此，接合焊盘的位置容易地被导电凸块的露出端识别和区分，使得导电迹线能够通过导电凸块与接合焊盘良好地电连接，以提高制造的封装的产量。

公开(公告)号：US06610560B2

公开(公告)日：2003-08-26

申请号：US09854303

申请日：2001-05-11

Applicant: Han-Ping Pu ,  Yu-Po Wang ,  Caesar Lin

Inventor： Han-Ping Pu ,  Yu-Po Wang ,  Caesar Lin

IPC: H01L2144

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L21/565 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A semiconductor packaging technology is proposed for the fabrication of a chip-on-chip (COC) based multi-chip module (MCM) with molded underfill. The proposed semiconductor packaging technology is characterized by the provision of a side gap of an empirically-predetermined width between the overlying chips mounted through COC technology over an underlying chip to serve as an air vent during molding process. This allows the injected molding material to flow freely into the flip-chip undergaps during molding process. In actual application, the exact width of the side gap is empirically predetermined through molded-underfill simulation experiments to find the optimal value. Based on experimental data, it is found that this side gap width should be equal to or less than 0.3 mm to allow optimal underfill effect. The optimal value for this side gap width may be varied for different package specifications.

公开(公告)号：US20130161837A1

公开(公告)日：2013-06-27

申请号：US13490810

申请日：2012-06-07

Applicant: Chia-Yin Chen ,  Yu-Ching Liu ,  Yueh-Chiung Chang ,  Yu-Po Wang

Inventor： Chia-Yin Chen ,  Yu-Ching Liu ,  Yueh-Chiung Chang ,  Yu-Po Wang

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/03 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/03462 ,  H01L2224/03552 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/27013 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Abstract translation: 提供了使用封装基板的封装基板和半导体封装。 封装基板包括：具有管芯附着区域的基板主体，形成在管芯附着区域周围的电路层，并且具有多个导线，每个导线具有引线焊盘，以及形成在引线接合焊盘上的表面处理层。 其中，仅有一个导电迹线连接到电镀线，以便防止由于现有技术中的电镀线太多导致的导电迹线之间的串扰。

公开(公告)号：US08304665B2

公开(公告)日：2012-11-06

申请号：US12266674

申请日：2008-11-07

Applicant: Chiang-Cheng Chang ,  Yen-Ping Wang ,  Don-Son Jiang ,  Jeng-Yuan Lai ,  Yu-Po Wang

Inventor： Chiang-Cheng Chang ,  Yen-Ping Wang ,  Don-Son Jiang ,  Jeng-Yuan Lai ,  Yu-Po Wang

IPC: H05K1/11 ,  H05K1/09 ,  H01R9/00

CPC classification number: H05K1/116 ,  H05K1/114 ,  H05K2201/09545 ,  H05K2201/09563

Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.

Abstract translation: 提出了具有无地导电迹线的封装衬底，其包括形成在其中的多个电镀通孔的芯层和形成在芯层的至少表面上的多个导电迹线。 每个导电迹线具有连接端，接合焊盘端和连接连接端和接合焊盘端的基体，导电迹线通过连接端电连接到相应的一个电镀通孔，以及 连接端具有大于基体的宽度，但不大于电镀通孔的直径，从而增加导电迹线和电镀通孔之间的接触面积，并且防止导电迹线的接触表面与 电镀通孔破裂。

公开(公告)号：US07816187B2

公开(公告)日：2010-10-19

申请号：US12204066

申请日：2008-09-04

Applicant: Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/00

CPC classification number: H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。