公开(公告)号：US20060018174A1

公开(公告)日：2006-01-26

申请号：US11169241

申请日：2005-06-27

Applicant: Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

Inventor： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4067

Abstract: Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

Abstract translation: 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 在所有存储区和当前刷新行完成自动刷新操作之前，允许该设备进入自刷新模式。 在继续对新行执行自刷新操作之前，内存设备完成当前刷新行的刷新操作。 描述和要求保护其他实施例。

公开(公告)号：US06826115B2

公开(公告)日：2004-11-30

申请号：US10640146

申请日：2003-08-13

Applicant: Jung-Bae Lee ,  Yun-Sang Lee

Inventor： Jung-Bae Lee ,  Yun-Sang Lee

IPC: G11C800

CPC classification number: G11C7/1021 ,  G11C8/10 ,  G11C8/12

Abstract: A semiconductor memory device having a partial activation framework, which provides an efficient page mode operation while operating in a partial activation mode. Control circuits and methods are provided to enable a page mode operation (for read and write data accesses) in a semiconductor memory device (such as a DRAM, FCRAM) having a partial activation framework, resulting in an improved data access speed when data is written/read from memory locations having the same wordline address. In one aspect, a method for accessing data in a memory device comprises activating a first wordline corresponding to a first address to perform a data access operation, receiving a second address after the first address, if the second address is the same as the first address, generating a page mode enable signal for maintaining an activated state of the first wordline corresponding to the first address while activating a second wordline corresponding to the second address, and deactivating the first and second wordlines in response to disabling of the page mode enable signal.

公开(公告)号：US06438042B1

公开(公告)日：2002-08-20

申请号：US09879076

申请日：2001-06-11

Applicant: Sang-Seok Kang ,  Yun-Sang Lee ,  Jong-Hyun Choi ,  Jae-Hoon Joo

Inventor： Sang-Seok Kang ,  Yun-Sang Lee ,  Jong-Hyun Choi ,  Jae-Hoon Joo

IPC: G11C700

CPC classification number: G11C11/4094 ,  G11C7/12 ,  H01L27/10897

Abstract: A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.

Abstract translation: 半导体存储器件包括第一和第二隔离晶体管，用于将一对位线与读出放大器电路电连接/隔离;以及MOS晶体管，其具有与第一和第二隔离晶体管的源极之一共享的源极区域。 MOS晶体管可以用作位线升压电容器。

公开(公告)号：US20130322162A1

公开(公告)日：2013-12-05

申请号：US13907223

申请日：2013-05-31

Applicant: YUN-SANG LEE ,  DONG-SEOK KANG ,  SANG-BEOM KANG ,  CHAN-KYUNG KIM ,  CHUL-WOO PARK ,  DONG-HYUN SOHN ,  HYUNG-ROK OH

Inventor： YUN-SANG LEE ,  DONG-SEOK KANG ,  SANG-BEOM KANG ,  CHAN-KYUNG KIM ,  CHUL-WOO PARK ,  DONG-HYUN SOHN ,  HYUNG-ROK OH

IPC: G11C11/16 ,  G11C7/12

CPC classification number: G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

Abstract: A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE)

Abstract translation: 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）

公开(公告)号：US20130148429A1

公开(公告)日：2013-06-13

申请号：US13705143

申请日：2012-12-04

Applicant: Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

Inventor： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC: G11C7/06 ,  G11C11/16 ,  G11C16/26 ,  G11C13/00

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06

Abstract: Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

Abstract translation: 提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。 第二开关被配置为接收第二CSL信号。 感测和锁存电路（SLC）耦合在第一和第二开关之间。 并且至少一个存储器单元耦合到第二开关。 第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。 存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。 还提供了使用这种存储器件执行读和写操作的方法。

公开(公告)号：US20130137944A1

公开(公告)日：2013-05-30

申请号：US13816035

申请日：2011-08-11

Applicant: Dae Hong Jeong ,  Keon Wook Kang ,  Dong Soo Lee ,  Yoon Sik Lee ,  Gun Sung Kim ,  Bong Hyun Jun ,  Jin Chul Paeng ,  Ho Young Lee ,  Yun Sang Lee

Inventor： Dae Hong Jeong ,  Keon Wook Kang ,  Dong Soo Lee ,  Yoon Sik Lee ,  Gun Sung Kim ,  Bong Hyun Jun ,  Jin Chul Paeng ,  Ho Young Lee ,  Yun Sang Lee

IPC: A61B5/00

CPC classification number: A61B5/0071 ,  A61B1/00165 ,  A61B1/00172 ,  A61B1/00186 ,  A61B1/015 ,  A61B1/043 ,  A61B1/063 ,  A61B1/126 ,  A61B5/0062 ,  A61B5/0068 ,  A61B5/0075 ,  A61B5/0084 ,  A61K49/0065 ,  B82Y30/00

Abstract: Method pertains to a medical imaging device for simultaneously detecting fluorescence and Raman signals for multiple fluorescence and Raman signal targets. The method includes: injecting at least one marker particle including Raman markers and receptors into the body of an animal, which can be a human; irradiating a laser beam onto the body of the animal; and detecting the optical signals emitted by the marker particle after the irradiation of the laser beam separately as fluorescence signals and Raman signals. The simultaneous detection of multiple targets may be performed even without scanning optical signals emitted by the marker particle individually with different optical fibers. As an examination may be performed by injecting surface-enhanced Raman marker particles, into which fluorescent components are introduced, into the body of the animal using a spray or the like, weak Raman signals may be augmented so as to obtain a more accurate diagnosis result in real time.

Abstract translation: 方法涉及用于同时检测多个荧光和拉曼信号靶的荧光和拉曼信号的医学成像装置。 该方法包括：将至少一种包括拉曼标记物和受体的标记物质注射到可以是人的动物体内; 将激光束照射到动物的身体上; 并且在激光束照射之后分别检测由标记物粒子发射的光信号作为荧光信号和拉曼信号。 即使不使用不同的光纤单独地扫描由标记颗粒发射的光信号，也可以执行多个目标的同时检测。 作为检查可以通过使用喷雾等将引入了荧光成分的表面增强拉曼标记颗粒注入动物的体内，可以增强弱拉曼信号，以获得更准确的诊断结果 实时。

公开(公告)号：US08042404B2

公开(公告)日：2011-10-25

申请号：US12128159

申请日：2008-05-28

Applicant: Young-Chan Jang ,  Jung-Bae Lee ,  Yun-Sang Lee

Inventor： Young-Chan Jang ,  Jung-Bae Lee ,  Yun-Sang Lee

IPC: G01L1/00

CPC classification number: G01R31/2849 ,  G01R31/2621 ,  G01R31/2642 ,  G11C29/12 ,  G11C29/50

Abstract: A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

Abstract translation: 应力检测电路包括功能块和检测信号生成电路。 功能块输出第一电压，使得第一电压根据功能块受应力的程度而变化。 检测信号发生电路在测试模式期间产生基于第一电压和第二电压的应力检测信号。 应力检测信号表示功能块的积分，第二电压的电平对应于在功能块受到应力之前的第一电压的电平。

公开(公告)号：US07894241B2

公开(公告)日：2011-02-22

申请号：US12326940

申请日：2008-12-03

Applicant: Yun-Sang Lee ,  Woo-Jung Sun ,  Jung-Bae Lee

Inventor： Yun-Sang Lee ,  Woo-Jung Sun ,  Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

Abstract: A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.

Abstract translation: 具有开放位线结构的存储单元阵列包括第一子存储单元阵列，第二子存储单元阵列，读出放大器/预充电电路，第一电容器和第二电容器。 第一子存储单元阵列响应于第一字线使能信号被激活，并且第二子存储单元阵列响应于第二字线使能信号被激活。 感测放大器/预充电电路通过第一位线连接到第一子存储单元阵列，并通过第二位线连接到第二子存储单元阵列，并且读出放大器/预充电电路对第一位线和第二位进行预充电 并且放大从第一子存储单元阵列和第二子存储单元阵列提供的数据。

公开(公告)号：US07734967B2

公开(公告)日：2010-06-08

申请号：US11863500

申请日：2007-09-28

Applicant: Hoe-ju Chung ,  Yun-sang Lee

Inventor： Hoe-ju Chung ,  Yun-sang Lee

IPC: G11C29/00

CPC classification number: G11C29/14 ,  G11C29/12015 ,  G11C2029/3602

Abstract: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

Abstract translation: 具有测试模式和正常模式的半导体存储器件包括倍频器和测试命令序列发生器。 倍频器在测试模式下接收测试时钟信号，并产生多个内部测试时钟信号，每个内部测试时钟信号的频率等于正常模式下的工作时钟信号的频率。 测试时钟信号的频率低于操作时钟信号的频率。 测试命令序列发生器响应于测试模式中的内部测试时钟信号而产生至少一个命令信号。 所述至少一个命令信号对应于待测量的半导体存储器件的至少一个操作定时参数。 倍频器可以包括锁相环（PLL）或延迟锁定环（DLL）。

公开(公告)号：US20080126876A1

公开(公告)日：2008-05-29

申请号：US11723473

申请日：2007-03-20

Applicant: Yun-Sang Lee

Inventor： Yun-Sang Lee

IPC: G06F11/00

CPC classification number: G06F11/1016 ,  G11C29/42 ,  G11C29/44 ,  G11C29/80 ,  G11C2029/0411 ,  G11C2029/1208

Abstract: A semiconductor memory device may include a memory cell array, a redundancy address decoder, a defective address detection unit, and a defective address program unit. The memory cell array includes a plurality of memory cell groups and a predetermined number of redundancy memory cell groups. The redundancy address decoder includes a predetermined number of redundancy decoders for accessing at least one group of the redundancy memory cell groups when a first defective address is identical to an externally applied address. The defective address detection unit performs a write operation and a read operation on the memory cell array during a test operation to detect a defective address, and outputs the detected defective address as the first defective address when the same defective address is detected a predetermined number of times or more. The defective address program unit receives and programs the first defective address output from the defective address detection unit during a program operation.

Abstract translation: 半导体存储器件可以包括存储单元阵列，冗余地址解码器，缺陷地址检测单元和缺陷地址程序单元。 存储单元阵列包括多个存储单元组和预定数量的冗余存储单元组。 冗余地址解码器包括预定数量的冗余解码器，用于当第一缺陷地址与外部施加的地址相同时，用于访问至少一组冗余存储单元组。 缺陷地址检测单元在测试操作期间对存储单元阵列执行写入操作和读取操作以检测缺陷地址，并且当检测到相同的缺陷地址时，将检测到的缺陷地址作为第一缺陷地址输出到预定数量的 次以上。 缺陷地址程序单元在编程操作期间接收并编程从缺陷地址检测单元输出的第一缺陷地址。