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公开(公告)号：US6122204A
公开(公告)日：2000-09-19
申请号：US320413
申请日：1999-05-26
CPC分类号： G11C7/065
摘要： A sense amplifier places a low positive voltage, such as 0.1 to 0.3 volts, on a bit line instead of ground when a memory cell is read by utilizing a current source circuit to output a reference current that biases a Schottky diode. The current source circuit is implemented with a Schottky diode that utilizes the reverse-biased leakage current of the diode to form the reference current. The current source circuit can also be implemented with a current mirror circuit.
摘要翻译： 当通过利用电流源电路读出存储单元以输出偏置肖特基二极管的参考电流时，读出放大器将位置线上的低正电压（例如0.1至0.3伏特）置于地线上而不是接地。 电流源电路用肖特基二极管实现，其利用二极管的反向偏置漏电流形成参考电流。 电流源电路也可以用电流镜电路来实现。
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22.发明授权Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages 失效采用具有CMOS兼容编程电压的单聚EPROM单元的存储器件
公开(公告)号：US6081451A
公开(公告)日：2000-06-27
申请号：US82145
申请日：1998-05-20
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/26 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/26 , H01L27/115 , H01L29/7887 , G11C2216/10 , G11C7/06
摘要： A memory device is disclosed which includes a plurality of memory cells formed in rows and columns. Each memory cell includes a Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor. A plurality of page lines are utilized to contact each memory transistor, while a plurality of enable lines are utilized to contact each access transistor.
摘要翻译： 公开了一种存储器件，其包括以行和列形成的多个存储单元。 每个存储单元包括一个Frohmann-Bentchkowsky p沟道存储晶体管和一个n沟道MOS存取晶体管。 利用多个页行来接触每个存储晶体管，同时使用多条使能线来接触每个存取晶体管。
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公开(公告)号：US6055185A
公开(公告)日：2000-04-25
申请号：US53309
申请日：1998-04-01
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0408 , G11C16/0433 , G11C16/10 , H01L27/115 , H01L29/7887 , G11C2216/10 , G11C7/06
摘要： The Frohmann-Bentchkowsky EPROM cell is programmed by utilizing biasing voltages which are sufficient to induce hot punchthrough holes to flow from the source region to the drain region, and insufficient to induce avalanche breakdown at the drain-to-semiconductor material junction. In addition, the Frohmann-Bentchkowsky EPROM cell is programmable with CMOS compatible voltages by forming the physical floating gate length of the cell to be less than the minimum physical gate length of the CMOS devices.
摘要翻译： 通过利用足以引起热穿透孔从源极区域流到漏极区域的偏置电压来编程Frohmann-Bentchkowsky EPROM单元，并且不足以在漏极 - 半导体材料结点处引起雪崩击穿。 此外，Frohmann-Bentchkowsky EPROM单元可通过将单元的物理浮置栅极长度小于CMOS器件的最小物理栅极长度来编程CMOS兼容电压。
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公开(公告)号：US6049202A
公开(公告)日：2000-04-11
申请号：US191140
申请日：1998-11-13
CPC分类号： G05F3/245
摘要： A reference current generator outputs a reference current which is insensitive to temperature variations by utilizing two gated diodes to output currents. The currents output by the gated diodes are divided to produce the reference current which, due to the cancellation of terms, is defined by the ratio of the gate areas of the gated diodes. In addition, by utilizing two oscillators, which run at different frequencies, to drive the gated diodes, the reference current may alternately be defined by the ratio of the two frequencies.
摘要翻译： 参考电流发生器通过利用两个门控二极管输出电流来输出对温度变化不敏感的参考电流。 由门控二极管输出的电流被分压以产生参考电流，由于术语的消除，其由门控二极管的栅极面积的比定义。 此外，通过利用以不同频率运行的两个振荡器来驱动门控二极管，参考电流可以交替地由两个频率的比率来定义。
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公开(公告)号：US5998267A
公开(公告)日：1999-12-07
申请号：US156940
申请日：1998-09-18
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/336 , H01L21/8236
CPC分类号： H01L27/112
摘要： A compact MOS array including word lines perpendicular to and overlapping bit lines, is fabricated by etching trenches in the underlying silicon and then forming successive bit lines within the trenches and upon the intervening mesas. Subsequent implantation of dopant into trench sidewalls creates channel regions oriented at an angle relative to the horizontal bit lines. Disposing successive diffused bit lines in vertically separated planes enables fabrication of ROM cells having full channel lengths which occupy a smaller surface area. Tilted ion implantation may be utilized to introduce dopant into channel regions.
摘要翻译： 通过蚀刻下面的硅中的沟槽，然后在沟槽内和中间的台面上形成连续的位线来制造包括垂直于和重叠的位线的字线的紧凑的MOS阵列。 随后将掺杂剂注入沟槽侧壁产生相对于水平位线成一定角度的沟道区。 在垂直分离的平面中布置连续的扩散位线使得能够制造具有占用较小表面积的全通道长度的ROM单元。 倾斜离子注入可用于将掺杂剂引入沟道区。
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26.发明授权Contact structure for improving photoresist adhesion on a dielectric layer 失效用于改善介电层上的光致抗蚀剂粘附性的接触结构
公开(公告)号：US5877541A
公开(公告)日：1999-03-02
申请号：US905918
申请日：1997-08-04
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L2924/0002 , Y10S257/90
摘要： A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.
摘要翻译： 提供了用于改善光致抗蚀剂层和电介质之间的粘合性的方法，以及根据该电路形成的集成电路。 在集成电路上形成保形介电层。 在保形电介质层上形成层间电介质层。 掺杂层间电介质层使得掺杂浓度允许层回流，同时部分地抑制掺杂层在掺杂层的上表面处的光致抗蚀剂的粘附。 在掺杂介电层上形成未掺杂的介电层。 在附着于未掺杂的介电层的未掺杂的电介质层上形成并图案化光致抗蚀剂层。 对未掺杂的电介质，层间电介质和共形绝缘层进行蚀刻以形成露出一部分下面的导电区域的开口。
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公开(公告)号：US5418174A
公开(公告)日：1995-05-23
申请号：US905020
申请日：1992-06-26
申请人： Alexander Kalnitsky
发明人： Alexander Kalnitsky
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/8234 , H01L29/51 , H01L21/266
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/3105 , H01L21/823462 , H01L29/51 , Y10S257/906 , Y10S257/921 , Y10S257/925 , Y10S438/953
摘要： A method is provided for forming a radiation hard dielectric region of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide region, a gate oxide layer and an interlevel dielectric layer are formed over the integrated circuit. Silicon ions are implanted separately into the field oxide region, gate oxide layer and interlevel dielectric layer to a sufficient dosage of less than or equal to approximately 1.times.10.sup.14 /cm.sup.2 to form electron traps to capture radiation induced electrons. This method allows for selective enhancement of radiation hardness of a portion of a circuit, thus providing an on-chip "dosimeter" which can be used to compensate the circuit for the loss of performance due to ionizing radiation.
摘要翻译： 提供一种用于形成半导体集成电路的辐射硬介电区域的方法和根据该集成电路形成的集成电路。 在集成电路上形成场氧化物区域，栅极氧化物层和层间电介质层。 将硅离子分别注入到场氧化物区域，栅极氧化物层和层间电介质层中，以足够的剂量小于或等于约1×10 14 / cm 2，以形成捕获辐射诱导电子的电子阱。 该方法允许选择性地增强电路的一部分的辐射硬度，从而提供片上“剂量计”，其可用于补偿电路由于电离辐射导致的性能损失。
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公开(公告)号：US4968641A
公开(公告)日：1990-11-06
申请号：US370319
申请日：1989-06-22
IPC分类号： H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76216 , Y10S438/911
摘要： In a method for the formation of an isolating oxide layer on a silicon substrate, an anti-nitridation layer is formed on a silicon substrate at locations where isolating oxide is desired. The anti-nitridation layer has openings therethrough which expose the silicon substrate at locations where isolating oxide is not desired. A thin silicon nitride layer is selectively grown at the locations where isolating oxide is not desired by nitridation of the exposed silicon substrate. Isolating oxide is then selectively grown at the locations where isolating oxide is desired. The thin silicon nitride layer inhibits oxide growth at the locations where isolating oxide is not desired. The method reduces "bird's beak" formation and is particularly applicable to high density IGFET devices.
摘要翻译： 在硅衬底上形成隔离氧化物层的方法中，在需要隔离氧化物的位置的硅衬底上形成抗氮化层。 抗氮化层具有穿过其的开口，在不需要隔离氧化物的位置处露出硅衬底。 通过暴露的硅衬底的氮化，在不需要隔离氧化物的位置选择性地生长薄氮化硅层。 然后在需要隔离氧化物的位置选择性地生长隔离氧化物。 薄氮化硅层在不需要隔离氧化物的位置抑制氧化物生长。 该方法减少了“鸟嘴”形成，特别适用于高密度IGFET装置。
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公开(公告)号：US09459234B2
公开(公告)日：2016-10-04
申请号：US13480161
申请日：2012-05-24
申请人： Alexander Kalnitsky , Yi-Shao Liu , Kai-Chih Liang , Chia-Hua Chu , Chun-Ren Cheng , Chun-Wen Cheng
发明人： Alexander Kalnitsky , Yi-Shao Liu , Kai-Chih Liang , Chia-Hua Chu , Chun-Ren Cheng , Chun-Wen Cheng
IPC分类号： H01L51/05 , G01N27/414 , H01L51/00
CPC分类号： G01N27/4145 , G01N27/414 , G01N27/4148 , H01L21/84 , H01L27/1203 , H01L51/0093
摘要： The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
摘要翻译： 本公开提供了生物场效应晶体管（BioFET）和制造BioFET器件的方法。 该方法包括使用与互补金属氧化物半导体（CMOS）工艺兼容或典型的一个或多个工艺步骤形成BioFET。 BioFET器件可以包括衬底; 设置在基板的第一表面上的栅极结构和形成在基板的第二表面上的界面层。 界面层可以允许将受体置于界面层上以检测生物分子或生物实体的存在。
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公开(公告)号：US08723123B2
公开(公告)日：2014-05-13
申请号：US13595743
申请日：2012-08-27
申请人： Alexander Kalnitsky , Chia-Hua Chu , Fei-Lung Lai , Chun-Wen Cheng , Chun-Ren Cheng , Yi-Hsien Chang
发明人： Alexander Kalnitsky , Chia-Hua Chu , Fei-Lung Lai , Chun-Wen Cheng , Chun-Ren Cheng , Yi-Hsien Chang
IPC分类号： G01J5/20
CPC分类号： G01J1/1626 , G01J1/4204 , G01J3/465 , H01L31/02164 , H01L31/103 , H01L31/105
摘要： A light detector includes a first light sensor and a second light sensor to detect incident light. A Ge film is disposed over the first light sensor to pass infra-red (IR) wavelength light and to block visible wavelength light. The Ge film does not cover the second light sensor.
摘要翻译： 光检测器包括第一光传感器和用于检测入射光的第二光传感器。 将Ge膜设置在第一光传感器上以通过红外（IR）波长的光并阻挡可见波长的光。 Ge膜不覆盖第二个光传感器。
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